Figure 9-1, Table 9-1, Gmii input setup/hold timing – Xilinx LOGICORE UG144 User Manual
Page 97
1-Gigabit Ethernet MAC v8.5 User Guide
97
UG144 April 24, 2009
Required Constraints
R
-- DISCONTINUED PRODUCT --
GMII Input Setup/Hold Timing
illustrate the setup and hold time window for the input GMII
signals. This is the worst-case data valid window presented to the FPGA device pins.
Observe that there is a 2 ns data valid window which is presented across the GMII input
bus. This must be correctly sampled by the FPGA devices.
The following constraints are provided in the UCF for GMII Example Designs. These
constraints invoke the tools to analyze the setup/hold requirements (though, if failing, the
tools are NOT capable of fixing them: meeting these constraints is a manual process - see
the following family specific sections for details):
INST "gmii_rxd<?>" TNM = IN_GMII;
INST "gmii_rx_er" TNM = IN_GMII;
INST "gmii_rx_dv" TNM = IN_GMII;
TIMEGRP "IN_GMII" OFFSET = IN 2.1 ns VALID 2.2 ns BEFORE "gmii_rx_clk";
The constraints defined in the preceding lines have a built-in 10% tolerance: this allows all
combinations of the example designs to pass timing. However, these should be tightened
in a real customer design as per the following syntax. Manual adjustments to IDELAY
values or DCM phase shift requirements may be required to meet these constraints (see the
following family specific sections for details).
TIMEGRP "IN_GMII" OFFSET = IN 2 ns VALID 2 ns BEFORE "gmii_rx_clk";
Spartan-3, Spartan-3E, Spartan-3A and Virtex-4 Devices
The GMII design uses a DCM on the receiver clock domain for Spartan-3, Spartan-3E,
Spartan-3A, and Virtex-4 devices. Phase-shifting is then applied to the DCM to align the
resultant clock so that it will correctly sample the 2 ns GMII data valid window at the input
flip-flops.
Figure 9-1:
Input GMII Timing
Table 9-1:
Input GMII Timing
Symbol
Min
Max
Units
t
SETUP
2.00
-
ns
t
HOLD
0.00
-
ns
t
SETUP
t
HOLD
GMII_RXD[7:0],
GMII_RX_DV,
GMII_RX_ER
GMII_RX_CLK