Chapter 11: interfacing to other cores – Xilinx LOGICORE UG144 User Manual

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1-Gigabit Ethernet MAC v8.5 User Guide

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UG144 April 24, 2009

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Chapter 11: Interfacing to Other Cores

Figure 11-1: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS with TBI 114
Figure 11-2: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS and PMA

using a RocketIO Transceiver

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 11-3: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS and PMA

using a RocketIO transceiver

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 11-4: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS and PMA

using the RocketIO transceiver

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 11-5: Interfacing the Ethernet Statistics to the 1-Gigabit Ethernet MAC . . . . . . 120

Chapter 12: Implementing Your Design

Appendix A: Using the Client-Side FIFO

Figure A-1: Typical 10 Mbps/100 Mbps/ 1 Gbps Ethernet FIFO Implementation . . . . . 127
Figure A-2: Frame Transfer across LocalLink Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure A-3: Frame Transfer with Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Appendix B: Core Verification, Compliance, and Interoperability

Appendix C: Calculating DCM Phase-Shifting

Appendix D: Core Latency

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