Xilinx LOGICORE UG144 - Manual (Page 106)

106 www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
Chapter 9: Constraining the Core R
-- DISCONTINUED PRODUCT --
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock rgmii_rxc
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
rgmii_rx_ctl| 0.810(R)| 0.933(R)| rgmii_rx_clk_bufg| 0.000|
| -3.214(F)| 4.959(F)| rgmii_rx_clk_bufg| 4.000|
rgmii_rxd<0>| 0.811(R)| 0.940(R)| rgmii_rx_clk_bufg| 0.000|
| -3.213(F)| 4.966(F)| rgmii_rx_clk_bufg| 4.000|
rgmii_rxd<1>| 0.801(R)| 0.946(R)| rgmii_rx_clk_bufg| 0.000|
| -3.223(F)| 4.972(F)| rgmii_rx_clk_bufg| 4.000|
rgmii_rxd<2>| 0.818(R)| 0.929(R)| rgmii_rx_clk_bufg| 0.000|
| -3.206(F)| 4.955(F)| rgmii_rx_clk_bufg| 4.000|
rgmii_rxd<3>| 0.809(R)| 0.936(R)| rgmii_rx_clk_bufg| 0.000|
| -3.215(F)| 4.962(F)| rgmii_rx_clk_bufg| 4.000|
------------+------------+------------+------------------+--------+
Virtex-5 Devices with Delayed Clock
Setup and Hold results for the RGMII input bus can be found in the data sheet section of
the Timing Report. However, depending on how the setup/hold requirements have been
met, it may not be immediately obvious how the results relate to
Figure 9-3 . Following is
an example for the RGMII report from a Virtex-5 device where the clock has been delayed
to meet the setup/hold requirements.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock rgmii_rxc
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
rgmii_rx_ctl| -7.178(R)| 8.880(R)| rgmii_rx_clk_bufg| 0.000|
| -11.178(F)| 12.880(F)| rgmii_rx_clk_bufg| 4.000|
rgmii_rxd<0>| -7.192(R)| 8.893(R)| rgmii_rx_clk_bufg| 0.000|
| -11.192(F)| 12.893(F)| rgmii_rx_clk_bufg| 4.000|
rgmii_rxd<1>| -7.182(R)| 8.884(R)| rgmii_rx_clk_bufg| 0.000|
| -11.182(F)| 12.884(F)| rgmii_rx_clk_bufg| 4.000|
rgmii_rxd<2>| -7.180(R)| 8.882(R)| rgmii_rx_clk_bufg| 0.000|
| -11.180(F)| 12.882(F)| rgmii_rx_clk_bufg| 4.000|
rgmii_rxd<3>| -7.179(R)| 8.881(R)| rgmii_rx_clk_bufg| 0.000|
| -11.179(F)| 12.881(F)| rgmii_rx_clk_bufg| 4.000|
------------+------------+------------+------------------+--------+
Each Input lists two sets of values—one corresponding to the +ve edge of the clock and one
to the –ve edge. The first set listed corresponds to +ve edge, which occurs at time 8 ns as we
have delayed the clock to use the following +ve edge.
The implementation requires –7.179 ns of setup to the +ve edge. Figure 9-4 illustrates that
this represents 0.821 ns relative to the following rising edge of the clock (since the IDELAY
has acted to delay the clock by an entire period when measured from the input flip-flop).