Xilinx LOGICORE UG144 - Manual (Page 72)

72 www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
Chapter 7: Using the Physical Side Interface R
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Virtex-4 Devices
Figure 7-8 shows using the physical receiver interface of the core to create an external
RGMII in a Virtex-4 device. The signal names and logic exactly match those delivered with
the example design when RGMII is selected.
Figure 7-8 also shows that the input receiver signals are registered in the IOBs in IDDR
components. These components convert the input double data rate signals into GMII
specification signals. The gmii_rx_er_int signal is derived in the FPGA fabric from
the outputs of the control IDDR component.
To achieve the required setup and hold times across the interface, the DCM uses a phase-
shift to adjust the clock relative to the data. See
Appendix C, “Calculating DCM Phase-
Shifting.”
DCM Reset circuitry
A DCM reset module, not illustrated in Figure 7-8 , is also present and is instantiated in the
example design next to the DCM. Since this logic must be reliable whatever the
reset/locked status of the DCM, the module requires a reliable reference clock. In the
example design for RGMII, a transmitter clock source is therefore used for this receiver
DCM. This is obtained from the BUFGMUX output which is connected to the DCM CLK90
output of
Figure 7-5 . The clock selection for this BUFGMUX will ensure that a 125MHz
clock is always present on this global clock route, even when the RGMII transmitter DCM
of
Figure 7-5 is held in reset itself.
This reset circuitry will generate an appropriate reset pulse for the receiver DCM of
Figure 7-8 under the following conditions:
•
The locked signal from the DCM is constantly monitored. Following a high to low
transition on this signal, indicating that the DCM has lost lock, a reset will be issued.
• A timeout counter is enabled when the DCM is in the loss of lock state. If, following
the timeout period, the DCM has not obtained lock, another DCM reset will be issued.
This timeout counter will time a > 1ms interval. This timeout functionality is required
for DCMs connected to Ethernet PHYs since the PHYs may source discontinuous
clocks under certain network conditions (for example, when no ethernet cable is
connected).
For Virtex-4 families, the generated reset from within the DCM reset module must be
asserted for a minimum of 200 ms (see the Virtex-4 Datasheet). Consequently, a 200 ms
duration timer is also included in the DCM reset module to extend the reset pulse. This
reset signal is output from the DCM reset module and should be routed to the DCM reset
input port.
Caution! In the example designs for Virtex-4 families, the 200ms reset pulse from the DCM
reset module is NOT connected directly to the DCM: this signal must be connected when
implementing the core in real hardware. The reason why the 200ms input is not routed directly to
the DCM is so that simulations can occur in a timely manner.
The 200ms reset pulse takes the signal name reset_200ms in the example design HDL
files. It is routed from the DCM reset module instantiation up through all levels of
hierarchy to the top level. It is then left unconnected in the example design instantiation
from within the demonstration test bench. Furthermore, an accompanying signal,
reset_200ms_in
, is routed down from the top level of the example design hierarchy to
the DCM instantiation, where it is connected to the DCM reset. From the demonstration
test bench, this reset_200ms_in signal is driven for a short duration to enable fast
simulation start up. However, to re-iterate, when implementing the design in real
hardware, the DCM reset signal must be connected correctly: