Period constraints for clock nets – Xilinx LOGICORE UG144 User Manual

Page 94

Advertising
background image

94

www.xilinx.com

1-Gigabit Ethernet MAC v8.5 User Guide

UG144 April 24, 2009

Chapter 9: Constraining the Core

R

-- DISCONTINUED PRODUCT --

PERIOD Constraints for Clock Nets

gtx_clk

The clock provided to gtx_clk must be constrained for a clock frequency of 125 MHz.

The following UCF syntax shows the necessary constraints being applied to the
gtx_clk

_bufg

signal

(which is routed to the gtx_clk

port of the core):

# Set the Transmitter clock period constraints: please do not relax

NET "gtx_clk_bufg" TNM_NET = "clk_tx";

TIMEGRP "tx_clock" = "clk_tx";

TIMESPEC "TS_tx_clk" = PERIOD "tx_clock" 8000 ps HIGH 50 %;

gmii_rx_clk (for GMII Example Designs)

The clock provided to

gmii_rx_clk

must be constrained for a clock frequency of 125 MHz.

The following UCF syntax shows the necessary constraints being applied to the clock

signal

(which is routed to the

gmii_rx_clk

port of the core)

# Set the Receiver clock period constraints: please do not relax

NET "gmii_rx_clk" TNM_NET = "gmii_rx_clk";

TIMESPEC "TS_gmii_rx_clk" = PERIOD "gmii_rx_clk" 8000 ps HIGH 50 %;

TIMEGRP "rx_clock" = "gmii_rx_clk";

rgmii_rxc (for RGMII Example Designs)

The receiver clock provided by the RGMII must be constrained for a clock frequency of 125
MHz.

The following UCF syntax shows the necessary constraints being applied to the clock

signal

(which is routed to the

gmii_rx_clk

port of the core):

# Set the Receiver clock period constraints: please do not relax

NET "gmii_rx_clk_bufg" TNM_NET = "clk_rx";

TIMEGRP "rx_clock" = "clk_rx";

TIMESPEC "TS_rx_clk" = PERIOD "rx_clock" 8000 ps HIGH 50 %;

host_clk

The clock provided to

host_clk

must be constrained to the desired frequency within the

allowable range (see

“Host Clock Frequency,” on page 77

).

The following UCF syntax shows a 100 MHz period constraint being applied to the
host_clk

signal

(which is routed to the host_clk

port of the core):

# Set the Management Clock period constraints: relax as required

NET "host_clk" TNM_NET = "host_clk";

TIMEGRP "host" = "host_clk" EXCEPT "mdio_logic";

TIMESPEC "TS_host_clk" = PERIOD "host" 10000 ps HIGH 50 %;

MDIO Logic

The MDIO logic (see

“MDIO Interface,” on page 30

) is synchronous to host_clk

,

but

data only changes at the mdc

output rate (as configured in the

“MDIO Configuration,” on

page 82

). Nominally mdc

will be set to a frequency of 2.5 MHz. Every flip-flop in the

MDIO logic is clocked with host_clk, but is sent a clock enable pulse at the mdc

frequency. To prevent this logic being over constrained by the host_clk

period, the

relevant flip-flops for the MDIO logic can be grouped together and removed from the
host_clk

period constraint. This is shown in the previous UCF syntax for host_clk

.

Advertising