Xilinx LOGICORE UG144 - Manual (Page 70)

70 www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
Chapter 7: Using the Physical Side Interface R
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The logic required to forward the transmitter clock is also shown. It has matching logic to
the data and control signals to provide a known relationship between the signals. An
IODELAY component is used to phase-shift the rgmii_txc clock signal by 90 degrees
with respect to gtx_clk_bufg. This allows the rising edge of rgmii_txc to occur in the
center of the data valid window—which maximizes setup and hold times across the
interface, as specified in the RGMII v2.0 specification. The IODELAY component is used in
fixed delay mode, where the attribute ODELAY_VALUE determines the tap delay value. An
IDELAYCTRL primitive must be instantiated for this mode of operation. See the Virtex-5
User Guide for more information on the use of IDELAYCTRL and IODELAY components.
RGMII Receiver Logic
Spartan-3, Spartan-3E, Spartan-3A and Spartan-3A DSP Devices
Figure 7-7 shows using the physical receiver interface of the core to create an external
RGMII in a Spartan-3 device. The signal names and logic exactly match those delivered
with the example design when the RGMII is selected. If other families are used, equivalent
primitives and logic specific to that family is used in the example design.
Figure 7-7 also shows that the input receiver signals are registered in device IOBs on rising
and falling edges of gmii_rx_clk_bufg. The signals are then registered inside the FPGA
fabric, before a final register stage to synchronize signals to the rising edge clock. To
achieve the required setup and hold times across the interface, the DCM uses a phase-shift
to adjust the clock relative to the data. See
Appendix C, “Calculating DCM Phase-
Shifting.”
DCM Reset circuitry
A DCM reset module, not illustrated in Figure 7-7 , is also present and is instantiated in the
example design next to the DCM. Since this logic must be reliable whatever the
reset/locked status of the DCM, the module requires a reliable reference clock. In the
example design for RGMII, a transmitter clock source is therefore used for this receiver
DCM.
This reset circuitry will generate an appropriate reset pulse for the receiver DCM of
Figure 7-7 under the following conditions:
• The locked signal from the DCM is constantly monitored. Following a high to low
transition on this signal, indicating that the DCM has lost lock, a reset will be issued.
•
A timeout counter is enabled when the DCM is in the loss of lock state. If, following
the timeout period, the DCM has not obtained lock, another DCM reset will be issued.
This timeout counter will time a > 1ms interval. This timeout functionality is required
for DCMs connected to Ethernet PHYs since the PHYs may source discontinuous
clocks under certain network conditions (for example, when no ethernet cable is
connected).
For Spartan-3 families, the reset pulse is transferred into the DCM input clock (rgmii_rxc
from
Figure 7-7 ). Here it is extended to three DCM clock periods duration and routed to
the reset input of the DCM.