Xilinx LOGICORE UG144 - Manual (Page 15)

1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com 15
UG144 April 24, 2009
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Preface
About This Guide
The LogiCORE™ IP 1-Gigabit Ethernet MAC User Guide provides information about
generating the core, customizing and simulating the core utilizing the provided example
design, and running the design files through implementation using the Xilinx tools.
Guide Contents
This guide contains the following chapters:
• Preface, “About this Guide” introduces the organization and purpose of the guide
and the conventions used in this document.
• Chapter 1, “Introduction” describes the core and related information, including
recommended design experience, additional resources, technical support, and
submitting feedback to Xilinx.
• Chapter 2, “Core Architecture” provides an overview of the core and discusses the
Physical/Client signal interfaces.
• Chapter 3, “Generating the Core” describes the graphical user interface options used
to generate the core.
•
Chapter 4, “Designing with the Core” through Chapter 8, “Configuration and Status”
describe design parameters, including how to initialize the core, generate and
consume core packets, and how to operate the Management Interface.
• Chapter 9, “Constraining the Core” describes the constraints associated with the core.
• Chapter 10, “Clocking and Resetting” discusses special design considerations
associated with clock management logic, including the Gigabit Media Independent
Interface (GMII) and Reduced Gigabit Media Independent Interface (RGMII) options.
• Chapter 11, “Interfacing to Other Cores” describes how to interface the 1-Gigabit
Ethernet MAC core to the Ethernet 1000BASE-X PCS/PMA or SGMII core and the
Ethernet Statistics core.
•
Chapter 12, “Implementing Your Design” provides instructions for how to set up
synthesis, simulation, and implementation environments and how to generate a
bitstream through the design flow.
• Appendix A, “Using the Client-Side FIFO” describes the FIFO provided in the
example design that accompanies the GEMAC core.
•
Appendix B, “Core Verification, Compliance, and Interoperability” describes how the
core was verified and certified for compliance.
• Appendix C, “Calculating DCM Phase-Shifting” provides information about how to
calculate the system timing requirements when using DCMs with the core.
• Appendix D, “Core Latency” describes the latency of the core.