Xilinx LOGICORE UG144 - Manual (Page 67)

1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com 67
UG144 April 24, 2009
Implementing External RGMII R
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Figure 7-4 shows that the output transmitter signals are registered on gtx_clk_bufg, in
the FPGA fabric, including the encoded rgmii_tx_ctl_int signal, derived from the
logical xor of gmii_tx_en_int and gmii_tx_er_int. The signals to be transmitted on
the RGMII falling clock edge are then registered on the falling edge of this clock. This
ensures that the data is presented to the Double Data Rate registers at the correct time.
Finally, the transmitter signals are registered by an IOB output Double-Data-Rate (DDR)
register before being driven to output pads.
The logic required to forward the transmitter clock is also shown. This uses an IOB output
DDR register so the clock signal produced incurs on exactly the same delay as the data and
control signals. The rgmii_tx_clk clock signal is phase-shifted by 90 degrees in the
DCM with respect to gtx_clk_bufg. This means that the rising edge of rgmii_txc
occurs in the center of the data valid window—which maximizes setup and hold times
across the interface, as specified in the Reduced Gigabit Media Independent Interface (RGMII)
Version 2.0 specification.
Virtex-4 Devices
Figure 7-5 shows using the physical transmitter interface of the core to create an external
RGMII in a Virtex-4 device. The signal names and logic shown exactly match those
delivered with the example design when the RGMII is selected
Figure 7-5 also shows that the output transmitter signals are registered in the IOBs in
ODDR components. These components convert the input signals into one double-data-rate
signal. These signals are then output through OBUFs before being driven to output pads.