Timespecs for critical logic within the core, Flow control, Configuration – Xilinx LOGICORE UG144 User Manual
Page 95
1-Gigabit Ethernet MAC v8.5 User Guide
95
UG144 April 24, 2009
Required Constraints
R
-- DISCONTINUED PRODUCT --
The UCF syntax which follows targets the MDIO logic flip-flops and groups them together.
Reduced clock period constraints are then applied.
############################################################
# MDIO Constraints: please do not edit #
############################################################
# Place the MDIO logic in it's own timing groups
INST "*gmac_core/BU2/U0/MANIFGEN?MANAGEN/PHY/ENABLE_REG" TNM = "mdc_rising";
INST "*gmac_core/BU2/U0/MANIFGEN?MANAGEN/PHY/READY_INT" TNM = "mdc_rising";
INST "*gmac_core/BU2/U0/MANIFGEN?MANAGEN/PHY/STATE_COUNT*" TNM = FFS "mdc_rising";
INST "*gmac_core/BU2/U0/MANIFGEN?MANAGEN/PHY/MDIO_TRISTATE" TNM = "mdc_falling";
INST "*gmac_core/BU2/U0/MANIFGEN?MANAGEN/PHY/MDIO_OUT" TNM = "mdc_falling";
TIMEGRP "mdio_logic" = "mdc_rising" "mdc_falling";
TIMESPEC "TS_mdio1" = PERIOD "mdio_logic" 400 ns;
TIMESPEC "TS_mdio2" = FROM "mdc_rising" TO "mdc_falling" 200 ns;
Timespecs for Critical Logic within the Core
Signals must cross clock domains at certain points in the core, as described in the following
sections.
Flow Control
Pause requests are received and decoding in the gmii_rx_clk domain and must be
transferred into the gtx_clk domain to pause the transmitter. Therefore, whenever
gmii_rx_clk
and gtx_clk are derived from different clock sources, the following
constraints must always be applied:
# Flow Control logic reclocking
INST "*gmac_core/BU2/U0/FLOW/RX_PAUSE/GOOD_FRAME_TO_TX" TNM="flow_rx_to_tx";
INST "*gmac_core/BU2/U0/FLOW/RX_PAUSE/PAUSE_REQ_TO_TX" TNM="flow_rx_to_tx";
INST "*gmac_core/BU2/U0/FLOW/RX_PAUSE_/AUSE_VALUE_TO_TX*" TNM="flow_rx_to_tx";
TIMESPEC "TS_flow_rx_to_tx" = FROM "flow_rx_to_tx" TO "tx_clock" 8000 ps;
Configuration
When the optional Management Interface is used with the core, configuration information
is written synchronously to host_clk. Receiver configuration data must be transferred
onto the gmii_rx_clk clock domain for use with the receiver and into the gtx_clk
clock domain for use with the transmitter. The following UCF syntax targets this logic and
a timing ignore attribute (TIG) is applied. It does not matter when configuration changes
take place—the current configurations are sampled between frames by both the receiver
and transmitter.
# Configuration Register reclocking
INST "*gmac_core/BU2/U0/MANIFGEN?MANAGEN/CONF/RX0_OUT*" TNM="config_to_rx";
INST "*gmac_core/BU2/U0/MANIFGEN?MANAGEN/CONF/RX1_OUT*" TNM="config_to_rx";
INST "*gmac_core/BU2/U0/MANIFGEN?MANAGEN/CONF/FC_OUT_29" TNM="config_to_rx";
TIMESPEC "TS_config_to_rx" = FROM "config_to_rx" TO "rx_clock" TIG;
INST "*gmac_core/BU2/U0/MANIFGEN?MANAGEN/CONF/TX_OUT*" TNM="config_to_tx";
INST "*gmac_core/BU2/U0/MANIFGEN?MANAGEN/CONF/FC_OUT_30" TNM="config_to_tx";
TIMESPEC "TS_config_to_tx" = FROM "config_to_tx" TO "tx_clock" TIG;