Xilinx LOGICORE UG144 - Manual (Page 73)

1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com 73
UG144 April 24, 2009
Implementing External RGMII R
-- DISCONTINUED PRODUCT --
• This can be achieved by connecting the reset_200ms signal to the
reset_200ms_in
signal at any level of example design HDL hierarchy.
Figure 7-8: External RGMII Receiver Logic for Virtex-4 Devices
1-Gigabit Ethernet MAC Core
gmii_rxd_int[0]
gmii_rx_dv_int
gmii_rx_er_int
gmii_rx_clk
gmii_rxd[0]
gmii_rx_dv
gmii_rx_er
BUFG
gmii_rx_clk_bufg
gmii_rxd_int[4]
gmii_rxd[4]
IOB LOGIC
rgmii_rx_ctl
IBUF
IDDR
IPAD
Q1
D Q2
C
IOB LOGIC
rgmii_rxd[0]
IBUF
IDDR
IPAD
Q1
D
Q2
C
rgmii_rxc
IBUFG
IOB LOGIC
IPAD
DCM
CLKIN CLK0
FB