Xilinx LOGICORE UG144 - Manual (Page 124)

124 www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
Chapter 12: Implementing Your Design R
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To synthesize the design, run:
$ xst -ifn top_level_module_name.scr
See the XST User Guide for more information on creating project and synthesis script files,
and running the xst program.
XST—Verilog
A module declaration for the GEMAC core is provided in the CORE Generator project
directory:
<component_name>/example_design/<component_name>_mod.v
Use this module to help instance the GEMAC core into your Verilog source.
After your entire design is complete, create:
• An XST project file top_level_module_name.prj listing all the user source code
files. Make sure you include
%XILINX%/verilog/src/iSE/unisim_comp.v
and
<component_name>/example_design/component_name_mod.v
as the first two files in the project list.
•
An XST script file top_level_module_name.scr containing your required
synthesis options.
To synthesize the design, run:
$ xst -ifn top_level_module_name.scr
See the XST User Guide for more information on creating project and synthesis script files,
and running the xst program.
Implementation
Generating the Xilinx Netlist
To generate the Xilinx netlist, the ngdbuild tools are used to translate and merge the
individual design netlists into a single design database, the NGD file. Also merged at this
stage is the UCF for the design.
An example of the ngdbuild command is:
$ ngdbuild -sd path_to_core_netlist -sd path_to_user_synth_results \
-uc top_level_module_name.ucf top_level_module_name
Mapping the Design
To map the logic gates of the user design netlist into the CLBs and IOBs of the FPGA, run
the map command. The map command writes out a physical design to an NCD file. An
example of the map command is:
$ map -o top_level_module_name_map.ncd top_level_module_name.ngd \
top_level_module_name.pcf