Xilinx LOGICORE UG144 - Manual (Page 61)

1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com 61
UG144 April 24, 2009
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Chapter 7
Using the Physical Side Interface
This chapter provides general guidelines for creating designs using the Physical Side
Interface of the GEMAC core. The physical side interface implements GMII-style signaling
and is typically attached to a physical layer device (PHY), either off-chip or internally
integrated. See
“Physical Side Interface” in Chapter 2 . For information about using an
internal interface in conjunction with the Ethernet 1000BASE-X PCS/PMA or SGMII core,
see
Chapter 11, “Interfacing to Other Cores.”
The remainder of this chapter describes how to use the core with an external GMII or
RGMII. See also
Chapter 9, “Constraining the Core” for a listing of required constraints.
Implementing External GMII
The HDL example design that is delivered with the core will implement an external GMII
when GMII is selected from the CORE Generator™ GUI (see
Chapter 3, “Generating the
Core” ). For more information about the example design, see the 1-Gigabit Ethernet MAC
Getting Started Guide.
GMII Transmitter Logic
Figure 7-1 illustrates how to use the physical transmitter interface of the core to create an
external GMII in a Spartan®-3 device. The signal names and logic shown in this figure
exactly match those delivered with the example design when the GMII is selected. If other
families are chosen, equivalent primitives and logic specific to that family is used in the
example design.
Figure 7-1 shows that the output transmitter signals are registered in device IOBs before
driving them to the device pads. The logic required to forward the transmitter clock is also
shown. This logic uses an IOB output Double-Data-Rate (DDR) register so that the clock
signal produced incurs exactly the same delay as the data and control signals. This clock
signal, gmii_tx_clk, is inverted with respect to gtx_clk so that the rising edge of
gmii_tx_clk
will occur in the centre of the data valid window, therefore maximizing
setup and hold times across the interface.