Xilinx 1000BASE-X - Manual (Page 81)

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 81
UG155 March 24, 2008
RocketIO Transceiver Logic R
Virtex-4 FX Devices
The core is designed to integrate with the Virtex-4 RocketIO MGT. Figure 7-2 illustrates the
connections and logic required between the core and MGT—the signal names and logic in
the figure precisely match those delivered with the example design when an MGT is used.
Note: A small logic shim (included in the block-level wrapper) is required to convert between the
port differences between the Virtex-II Pro and Virtex-4 RocketIO transceivers.
The MGT clock distribution in Virtex-4 devices is column-based and consists of multiple
MGT tiles (each tile contains two MGTs). For this reason, the MGT wrapper delivered with
the core always contains two MGT instantiations, even if only a single MGT is in use.
Figure 7-2 illustrates a single MGT tile for clarity.
A GT11CLK_MGT primitive is also instantiated to derive the reference clocks required by
the MGT column-based tiles. See the Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide
(UG076) for information about layout and clock distribution.
The 250 MHz reference clock from the GT11CLK_MGT primitive is routed to the MGT,
configured to internally synthesize a 125 MHz clock. This is output on the TXOUTCLK1
port of the MGT and after placed onto global clock routing, can be used by all core logic.
This clock is input back into the MGT on the user interface clock ports rxusrclk2 and
txusrclk2
. With the attribute settings applied to the MGT from the example design, the
txusrclk and rxusrclk ports are derived internally within the MGT using the internal
clock dividers and do not need to be provided from the FPGA fabric.
The Virtex-4 FX MGTs require the inclusion of a calibration block in the fabric logic; the
example design provided with the core instantiates calibration blocks as required.
Calibration blocks require a clock source of between 25 to 50 MHz that is shared with the
Dynamic Reconfiguration Port (DRP) of the MGT, which is named dclk in the example
design. See Xilinx
Answer Record 22477 for more information.
Figure 7-2 also illustrates the TX_SIGNAL_DETECT and RX_SIGNAL_DETECT ports of the
calibration block, which should be driven to indicate whether or not dynamic data is being
transmitted and received through the MGT (see
Virtex-4 Errata ). However,
RX_SIGNAL_DETECT is connected to the signal_detect port of the example design.
signal_detect is intended to be connected to the optical transceiver to indicate the
presence of light. When light is detected, the optical transceiver provides dynamic data to
the Rx ports of the MGT. When no light is detected, the calibration block switches the MGT
into loopback to force dynamic data through the MGT receiver path.
Caution! signal_detect is an optional port in the IEEE 802.3 specification. If this is not
used, the RX_SIGNAL_DETECT port of the calibration block must be driven by an alternative
method. Please refer to XAPP732 for more information.