Xilinx 1000BASE-X - Manual (Page 183)

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 183
UG155 March 24, 2008
Integrating with the 1-Gigabit Ethernet MAC Core R
Features of this configuration include:
•
Direct internal connections are made between the GMII interfaces between the two
cores.
•
If both cores have been generated with the optional management interface, the MDIO
port can be connected up to that of the 1-Gigabit Ethernet MAC core, allowing the
MAC to access the embedded configuration and status registers of the Ethernet
1000BASE-X PCS/PMA or SGMII core.
•
Due to the embedded Receiver Elastic Buffer in the MGT, the entire GMII is
synchronous to a single clock domain. Therefore userclk2 is used as the 125 MHz
reference clock for both cores, and the transmitter and receiver logic of the 1-Gigabit
Ethernet MAC core now operate in the same clock domain.
Virtex-5 LXT and SXT Devices
Figure 13-4 illustrates the connections and clock management logic required to interface
the Ethernet 1000BASE-X PCS/PMA or SGMII core (when used in 1000BASE-X mode) to
the 1-Gigabit Ethernet MAC core.
Figure 13-4: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS and
PMA Using a Virtex-5 GTP Transceiver
1-Gigabit Ethernet
MAC
LogiCORE
gmii_rx_clk
gmii_rxd[7:0]
gmii_rx_dv
gmii_rx_er
gmii_txd[7:0]
gmii_tx_en
gmii_tx_er
gtx_clk
mdc
mdio_in
mdio_out
mdio_tri
Ethernet 1000BASE-X
PCS/PMA or SGMII
LogiCORE
gmii_rxd[7:0]
gmii_rx_dv
gmii_rx_er
gmii_txd[7:0]
gmii_tx_en
gmii_tx_er
mdc
mdio_in
mdio_out
mdio_tri
Virtex-5
GTP
RocketIO
no
connection
userclk
userclk2
RocketIO I/F
CLKIN
userclk2
(125 MHz)
TXUSRCLK0
TXUSRCLK20
RXUSRCLK0
RXUSRCLK20
BUFG
REFCLKOUT
component_name_block
(Block Level from example design)
clkin
(125MHz)
IBUFGDS
IPAD
brefclkp
IPAD
brefclkn