Xilinx 1000BASE-X - Manual (Page 87)

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 87
UG155 March 24, 2008
Clock Sharing Across Multiple Cores with RocketIO R
Clock Sharing Across Multiple Cores with RocketIO
Virtex-II Pro Devices
Figure 7-5 illustrates sharing clock resources across two instantiations of the core on the
same half of the device when using the core with the Virtex-II Pro MGT. Note that more can
be added by instantiating the cores using the block level (from the example design) and
continuing to share userclk, userclk2, and brefclk across all instantiations. For each
core, userclk and userclk2 must always be derived from the brefclk or refclk used
by that core.
When using the fixed routing resources of brefclk, MGTs along the top edge of the
device must use a separate brefclk routing resource to those along the bottom edge of
the device. For more information, see the Virtex-II Pro RocketIO Transceiver User Guide
(UG024). Each brefclk domain must use its own DCM to derive its version of userclk
and userclk2.
Figure 7-5: Clock Management: Two Core Instances, Virtex-II Pro
MGTs for 1000BASE-X
DCM
CLKIN CLK0
CLK2X180 FB
BUFG
BUFG
IBUFGDS
TXUSRCLK
BREFCLK
TXUSRCLK2
RXUSRCLK
RXUSRCLK2
GT_ETHERNET_1
brefclk (62.5MHz)
userclk (62.5 MHz)
userclk2 (125 MHz)
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
Customer Design
userclk
userclk2
TXUSRCLK
BREFCLK
TXUSRCLK2
RXUSRCLK
RXUSRCLK2
GT_ETHERNET_1 Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
IPAD
brefclkp
IPAD
brefclkn
component_name_block
(Block Level)
component_name_block
(Block Level)