Xilinx 1000BASE-X - Manual (Page 161)

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 161
UG155 March 24, 2008
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Chapter 12
Constraining the Core
This chapter defines the constraint requirements of the Ethernet 1000BASE-X PCS/PMA or
SGMII core. An example UCF is provided with the HDL example design for the core to
implement the constraints defined in this chapter.
See the Ethernet 1000BASE-X PCS/PMA or SGMII Getting Started Guide for a complete
description of the CORE Generator output files and for details on the HDL example
design.
Required Constraints
Device, Package, and Speedgrade Selection
The Ethernet 1000BASE-X PCS/PMA or SGMII core can be implemented in Virtex-II,
Virtex-II Pro, Virtex-4, Virtex-5, Spartan-3, Spartan-3E, Spartan-3A, Spartan-3AN and
Spartan-3 DSP devices. When selecting a device, be aware of the following considerations:
•
Device must be large enough to accommodate the core
•
Device must contain a sufficient number of IOBs
•
–4 speed grade for Virtex-II, Spartan-3, Spartan-3E, Spartan-3A, Spartan-3AN and
Spartan-3A DSP devices
•
–5 speed grade for Virtex-II Pro FPGA
•
–10 speed grade for Virtex-4 FPGA
•
-1 speed grade for Virtex-5 FPGA
•
The RocketIO transceiver is only supported in Virtex-II Pro, Virtex-4 FX, Virtex-5 LXT,
Virtex-5 SXT, and Virtex-5 FXT FPGAs
I/O Location Constraints
No specific I/O location constraints required.
Placement Constraints
No specific placement constraints required.
Virtex-II Pro RocketIO MGTs for 1000BASE-X Constraints
The constraints defined in this section are implemented in the UCF for the example
designs delivered with the core. Sections from the UCF are copied into the descriptions in
the following sections to serve as examples. These should be studied in conjunction with