Xilinx 1000BASE-X - Manual (Page 52)

52 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
Chapter 4: Designing with the Core R
Keep it Registered
To simplify timing and to increase system performance in an FPGA design, keep all inputs
and outputs registered between the user application and the core. All inputs and outputs
from the user application should come from, or connect to, a flip-flop. While registering
signals may not be possible for all paths, it simplifies timing analysis and makes it easier
for the Xilinx tools to place and route the design.
Recognize Timing Critical Signals
The UCF provided with the example design for the core identifies the critical signals and
the timing constraints that should be applied. See
Chapter 12, “Constraining the Core” for
more information.
Use Supported Design Flows
The core is pre-synthesized and is delivered as an NGC netlist. The example
implementation scripts provided currently uses ISE 10.1 as the synthesis tool for the HDL
example design delivered with the core. Other synthesis tools may be used for the user
application logic. The core will always be unknown to the synthesis tool and should
appear as a black box. Post synthesis, only ISE 10.1i tools are supported.
Make Only Allowed Modifications
The Ethernet 1000BASE-X PCS/PMA or SGMII core should not be modified. Modifications
may have adverse effects on system timing and protocol compliance. Supported user
configurations of the Ethernet 1000BASE-X PCS/PMA or SGMII core can only be made by
the selecting the options from within CORE Generator when the core is generated. See
Chapter 3, “Generating and Customizing the Core.”
Spartan-3E Difficult
Spartan-3A Difficult
Table 4-1: Degree of Difficulty for Various Implementations
Device Family Difficulty