Xilinx 1000BASE-X - Manual (Page 48)

48 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
Chapter 4: Designing with the Core R
SGMII Standard Using a RocketIO Transceiver Example Design
Figure 4-3 illustrates the example design in SGMII mode using the Virtex-II Pro or Virtex-
4 MGT, Virtex-5 GTP or Virtex-5 GTX transceiver. This is also the example design created
when the Dynamic Switching capability between SGMII and 1000BASE-X standards is
present. As illustrated, the example is split between two hierarchical layers. The block level
is designed so that it can be instantiated directly into customer designs and performs the
following functions:
•
Instantiates the core from HDL
•
Connects the physical-side interface of the core to a RocketIO transceiver
•
Connects the client side GMII of the core to an SGMII Adaptation Module, which
provides the functionality to operate at speeds of 1 Gbps, 100 Mbps and 10 Mbps
The top level of the example design creates a specific example which can be simulated,
synthesized and implemented. The top level of the example design performs the following
functions:
•
Instantiates the block level from HDL
•
Derives the clock management logic for RocketIO and the core
•
Implements an external GMII-style interface
Figure 4-3: Example Design Performing the SGMII Standard
Ethernet
1000BASE-X
PCS/PMA
Core
GMII
IOBs
In
IOBs
Out
GMII-style
8-bit I/F
Serial GMII
(SGMII)
SGMII
Adaptation
Module
Clock
Management
Logic
Transceiver
Fabric
Rx
Elastic
Buffer
RocketIO
component_name_example_design
component_name_block