Figure 7-8, A gtx tile, Clock sharing across multiple cores with rocketio – Xilinx 1000BASE-X User Manual
Page 93
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
93
UG155 March 24, 2008
Clock Sharing Across Multiple Cores with RocketIO
R
Figure 7-8:
Clock Management - Multiple Core Instances, Virtex-5 RocketIO GTX
Transceivers for 1000BASE-X
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
Virtex-5
GTP
RocketIO
(0)
CLKIN
rocketio_wrapper_gtp_tile
Virtex-5
GTP
RocketIO
(1)
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
TXUSRCLK0
TXUSRCLK20
RXUSRCLK0
RXUSRCLK20
TXUSRCLK1
TXUSRCLK21
RXUSRCLK1
RXUSRCLK21
clkin
(125MHz)
REFCLKOUT
component_name_block
(Block Level)
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
Virtex-5
GTP
RocketIO
(0)
Virtex-5
GTP
RocketIO
(1)
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
TXUSRCLK0
TXUSRCLK20
RXUSRCLK0
RXUSRCLK20
TXUSRCLK1
TXUSRCLK21
RXUSRCLK1
RXUSRCLK21
REFCLKOUT
component_name_block
(Block Level)
NC
IBUFGDS
IPAD
brefclkp
IPAD
brefclkn
CLKIN
rocketio_wrapper_gtp_tile
rocketio_wrapper_gtp
rocketio_wrapper_gtp
userclk2 (125MHz)
DCM
CLKIN CLK0
FB
BUFG
CLKDV
BUFG
userclk (62.5MHz)