Xilinx 1000BASE-X - Manual (Page 135)

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 135
UG155 March 24, 2008
Management Registers R
SGMII Standard Using the Optional Auto-Negotiation
The registers provided for SGMII operation in this core are adaptations of those defined in
IEEE 802.3 clauses 37 and 22. In an SGMII implementation, two different types of links
exist. They are the SGMII link between the MAC and PHY (SGMII link) and the link across
the Ethernet Medium itself (Medium). See
Figure 10-2 .
Information regarding the state of both of these links is contained within the following
registers. Where applicable, the abbreviations SGMII link and Medium are used in the
register descriptions. Registers at undefined addresses are read-only and return 0s.
Register 0: SGMII Control
Table 9-18: MDIO Registers for 1000BASE-X with Auto-Negotiation
Register Address Register Name
0 SGMII Control Register
1 SGMII Status Register
2,3 PHY Identifier
4 SGMII Auto-Negotiation Advertisement Register
5 SGMII Auto-Negotiation Link Partner Ability Base Register
6 SGMII Auto-Negotiation Expansion Register
7 SGMII Auto-Negotiation Next Page Transmit Register
8 SGMII Auto-Negotiation Next Page Receive Register
15 SGMII Extended Status Register
16 SGMII Vendor Specific: Auto-Negotiation Interrupt Control
MDIO Register 0: SGMII Control
RESET LOOPBA
CK
A
U
T
O-NEG ENABLE
REST
AR
T A
U
T
O-NEG
RESER
VED
PO
WER DO
WN
SPEED SPEED
15 14 13 12 11 10 7 6 5 0
Reg 0
ISOLA
TE
9 8
DUPLEX MODE COLLISION TEST
4
UNIDIRECTIONAL ENABLE