Xilinx 1000BASE-X - Manual (Page 177)

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 177
UG155 March 24, 2008
Required Constraints R
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock gmii_tx_clk
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
gmii_tx_en | -6.501(R)| 7.875(R)|gmii_tx_clk_bufg | 0.000|
gmii_tx_er | -6.504(R)| 7.878(R)|gmii_tx_clk_bufg | 0.000|
gmii_txd<0> | -6.506(R)| 7.880(R)|gmii_tx_clk_bufg | 0.000|
gmii_txd<1> | -6.521(R)| 7.893(R)|gmii_tx_clk_bufg | 0.000|
gmii_txd<2> | -6.518(R)| 7.890(R)|gmii_tx_clk_bufg | 0.000|
gmii_txd<3> | -6.515(R)| 7.889(R)|gmii_tx_clk_bufg | 0.000|
gmii_txd<4> | -6.521(R)| 7.894(R)|gmii_tx_clk_bufg | 0.000|
gmii_txd<5> | -6.520(R)| 7.895(R)|gmii_tx_clk_bufg | 0.000|
gmii_txd<6> | -6.514(R)| 7.889(R)|gmii_tx_clk_bufg | 0.000|
gmii_txd<7> | -6.513(R)| 7.889(R)|gmii_tx_clk_bufg | 0.000|
------------+------------+------------+------------------+--------+
The implementation requires -6.501 ns of setup. Figure 12-4 illustrates that this represents
a figure of 1.499 ns relative to the following rising edge of the clock (because the IDELAY
has acted to delay the clock by an entire period when measured from the input flip-flop).
This is less than the 2 ns required, and so there is slack.
The implementation requires 7.893 ns of hold. Figure 12-4 illustrates that this represents a
figure of -0.107 ns relative to the following rising edge of the clock (because the IDELAY
has acted to delay the clock by an entire period when measured from the input flip-flop).
This is less than the 0 ns required, and so there is slack.
Figure 12-4: Timing Report Setup/Hold Illustration
t
SETUP
t
HOLD
GMII_TXD[7:0],
GMII_TX_EN,
GMII_TX_ER
GMII_TX_CLK
8 ns
-6.501 ns
= 8 - 6.501
= 1.499 ns
8 ns
7.893 ns
= 7.893 - 8
= -0.107 ns