Figure 8-8, These – Xilinx 1000BASE-X User Manual
Page 110
110
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
Chapter 8: SGMII / Dynamic Standards Switching with RocketIO Transceivers
R
Figure 8-8:
Clock Management with Multiple Core Instances with Virtex-4 MGTs for
SGMII
component_name_block
(Block Level)
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
IPAD
brefclkp
(250MHz)
IPAD
brefclkn
(250MHz)
Virtex-4
GT11CLK_MGT
MGTCLKP
MGTCLKN
SYNCLK1OUT
Virtex-4
GT11
RocketIO
(A)
REFCLK1
MGT tile
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
NC
userclk2
(125 MHz)
TXUSRCLK
TXUSRCLK2
RXUSRCLK
RXUSRCLK2
synclk1
(250MHz)
‘0’
‘0’
‘0’
‘0’
TXOUTCLK1
RXRECCLK1
FPGA
fabric
Rx
Elastic
Buffer
BUFR
Virtex-4
GT11
RocketIO
(B)
REFCLK1
TXUSRCLK
TXUSRCLK2
RXUSRCLK
RXUSRCLK2
TXOUTCLK1
RXRECCLK1
FPGA
fabric
Rx
Elastic
Buffer
BUFR
BUFG
component_name_block
(Block Level)
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
Virtex-4
GT11
RocketIO
(A)
REFCLK1
MGT tile
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
NC
userclk2
(125 MHz)
TXUSRCLK
TXUSRCLK2
RXUSRCLK
RXUSRCLK2
‘0’
‘0’
‘0’
‘0’
TXOUTCLK1
RXRECCLK1
FPGA
fabric
Rx
Elastic
Buffer
BUFR
Virtex-4
GT11
RocketIO
(B)
REFCLK1
TXUSRCLK
TXUSRCLK2
RXUSRCLK
RXUSRCLK2
TXOUTCLK1
RXRECCLK1
FPGA
fabric
Rx
Elastic
Buffer
BUFR
NC