Xilinx 1000BASE-X - Manual (Page 90)

90 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
Chapter 7: 1000BASE-X with RocketIO Transceivers R
Virtex-5 LXT and SXT Devices
Figure 7-7 illustrates sharing clock resources across multiple instantiations of the core
when using Virtex-5 RocketIO GTP transceivers.
The example design can be generated to connect either a single instance of the core or
connect a pair of core instances to the transceiver pair present in a GTP tile.
Figure 7-7
illustrates two instantiations of the block level, and each block level contains a pair of
cores, consequently illustrating clock sharing between a total of four cores.
Additional cores can be added by continuing to instantiate extra block level modules.
Share the brefclk_p and brefclk_n differential clock pair. See the Virtex-5 RocketIO
GTP Transceiver User Guide (UG196) for more information.
To provide the 125 MHz clock for all core instances, select a REFCLKOUT port from any
GTP transceiver. This can be routed onto global clock routing using a BUFG as illustrated
and shared between all cores and GTP transceivers.