Xst - verilog, Implementation, Generating the xilinx netlist – Xilinx 1000BASE-X User Manual

Page 202: Mapping the design, Placing and routing the design

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Ethernet 1000BASE-X PCS/PMA or SGMII v9.1

UG155 March 24, 2008

Chapter 15: Implementing the Design

R

See the XST User Guide for more information on creating project and synthesis script files,
and running the xst program.

XST - Verilog

There is a module declaration for the Ethernet 1000BASE-X PCS/PMA or SGMII core in the
CORE Generator project directory:

<

component_name>/implement/<component_name>_mod.v

Use this module to help instance the Ethernet 1000BASE-X PCS/PMA or SGMII core into
your Verilog source.

After the entire design is complete, do the following:

Generate an XST project file

top_level_module_name

.prj

listing all user source

code files.

Make sure to include the following as the first two files in the project list.

%XILINX%/verilog/src/iSE/unisim_comp.v

and

<component_name>/implement/component_name_mod.v

Generate an XST script file

top_level_module_name

.scr

containing your

required synthesis options.

To synthesize the design, run:

$ xst -ifn top_level_module_name.scr

See the XST User Guide for more information on creating project and synthesis script files,
and running the xst program.

Implementation

Generating the Xilinx Netlist

To generate the Xilinx netlist, the ngdbuild tools is used to translate and merge the
individual design netlists into a single design database—the NGD file. Also merged at this
stage is the UCF for the design. An example of the ngdbuild command is:

$ ngdbuild -sd path_to_core_netlist -sd path_to_user_synth_results \

-uc top_level_module_name.ucf top_level_module_name

Mapping the Design

To map the logic gates of the user design netlist into the CLBs and IOBs of the FPGA, run
the map command. The map command writes out a physical design to an NCD file. An
example of the map command is:

$ map -o top_level_module_name_map.ncd top_level_module_name.ngd \

top_level_module_name.pcf

Placing and Routing the Design

The par command must be executed to place and route the user’s design logic
components (mapped physical logic cells) within an NCD file, in accordance with the

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