Signal integrity correlation results, Figure 7-2 – Xilinx Virtex-5 FPGA ML561 User Manual
Page 58
58
Virtex-5 FPGA ML561 User Guide
UG199 (v1.2.1) June 15, 2009
Chapter 7: ML561 Hardware-Simulation Correlation
R
♦
DDR2 mask (for nominal VDDQ = 1.8V and VREF = 0.9V):
-
VIH(ac)-min = VREF + 200 mV = 1.1V
-
VIH(dc)-min = VREF + 125 mV = 1.025V
-
VIL(ac)-max = VREF – 200 mV = 0.7V
-
VIL(dc)-max = VREF – 125 mV = 0.775V
♦
QDRII mask (for nominal values of VDDQ = 1.8V and VREF = 0.9V):
-
VIH(ac)-min = VREF + 200 mV = 1.1V
-
VIH(dc)-min = VREF + 100 mV = 1.0V
-
VIL(ac)-max = VREF – 200 mV = 0.7V
-
VIL(dc)-max = VREF – 100 mV = 0.8V
Signal Integrity Correlation Results
This section presents SI results for each of the six chosen memory signals on the ML561
board. The following information is presented for each memory signal:
•
A post-layout IBIS schematics of the signal under test
•
A description of the major circuit elements
(1)
of this signal
•
A summary of four SI results: hardware measurement, correlation simulation, slow-
weak corner driver simulation extrapolation, and fast-strong corner driver simulation
extrapolation
•
A set of eight figures showing eye and waveform scope shots for each of the four SI
results mentioned in the bulleted list in the previous section
For an explanation of the different terms used to present these results, refer to
for some definitions and routing terminologies.
Figure 7-2:
Two Triangular Eye Mask Definitions for VIH and VIL
VOH(dc)
VOL(dc)
VOH(ac)
VOL(ac)
UG199_c7_02_062707
VIH(ac)
VIL(ac)
VIH(dc)
VIL(dc)
VDDQ
VSS
VREF
1. With regard to transmission line impedance,
in the
section lists
controlled impedance values of all routing layers. The design goal for the ML561 board is to keep the
characteristic impedance for all routing layers as close to 50
Ω as possible. Manufacturing tolerance is usually
±10%. The characteristic impedance of DIMM PCB is derived from the Micron DIMM layout file.