Xilinx Virtex-5 FPGA ML561 - Manual (Page 100)

100 www.xilinx.com Virtex-5 FPGA ML561 User Guide
UG199 (v1.2.1) June 15, 2009
Appendix A: FPGA Pinouts R
FPGA #2 Pinout
Table A-2 lists the connections for FPGA #2 (U5).
Table A-2: FPGA #2 Pinout
Signal Name Pin Signal Name Pin
DDR2 DIMM Deep Interface
DDR2_DIMM_A0 AG30 DDR2_DIMM1_CK0_N M26
DDR2_DIMM_A1 AH29 DDR2_DIMM1_CK0_P M25
DDR2_DIMM_A10 AF31 DDR2_DIMM1_CK1_N J25
DDR2_DIMM_A11 AC29 DDR2_DIMM1_CK1_P J24
DDR2_DIMM_A12 AD30 DDR2_DIMM1_CK2_N L26
DDR2_DIMM_A13 AA30 DDR2_DIMM1_CK2_P L25
DDR2_DIMM_A14 AA29 DDR2_DIMM1_CKE0 G28
DDR2_DIMM_A15 AC30 DDR2_DIMM1_CKE1 H28
DDR2_DIMM_A2 AH30 DDR2_DIMM1_CS0_N V27
DDR2_DIMM_A3 AJ30 DDR2_DIMM1_CS1_N V28
DDR2_DIMM_A4 AF30 DDR2_DIMM1_ODT0 H24
DDR2_DIMM_A5 AF29 DDR2_DIMM1_ODT1 H25
DDR2_DIMM_A6 AK31 DDR2_DIMM2_CK0_N AF26
DDR2_DIMM_A7 AJ31 DDR2_DIMM2_CK0_P AF25
DDR2_DIMM_A8 AD29 DDR2_DIMM2_CK1_N AG25
DDR2_DIMM_A9 AE29 DDR2_DIMM2_CK1_P AF24
DDR2_DIMM_BA0 AB30 DDR2_DIMM2_CK2_N AJ26
DDR2_DIMM_BA1 AA31 DDR2_DIMM2_CK2_P AH27
DDR2_DIMM_BA2 AB31 DDR2_DIMM2_CKE0 AE24
DDR2_DIMM_CAS_N V29 DDR2_DIMM2_CKE1 AD24
DDR2_DIMM_LB_BK11_IN P32 DDR2_DIMM2_CS0_N W27
DDR2_DIMM_LB_BK11_OUT H33 DDR2_DIMM2_CS1_N Y27
DDR2_DIMM_LB_BK13_IN AJ32 DDR2_DIMM2_ODT0 AE26
DDR2_DIMM_LB_BK13_OUT AK32 DDR2_DIMM2_ODT1 AE27
DDR2_DIMM_LB_BK15_IN T28 DDR2_DIMM3_CK0_N AA24
DDR2_DIMM_LB_BK15_OUT T29 DDR2_DIMM3_CK0_P Y24
DDR2_DIMM_RAS_N Y28 DDR2_DIMM3_CK1_N AC27
DDR2_DIMM_RESET_N Y29 DDR2_DIMM3_CK1_P AB27
DDR2_DIMM_WE_N W29 DDR2_DIMM3_CK2_N AA26