Xilinx Virtex-5 FPGA ML561 - Manual (Page 105)

Virtex-5 FPGA ML561 User Guide www.xilinx.com 105
UG199 (v1.2.1) June 15, 2009
FPGA #2 Pinout R
DDR2 DIMM Miscellaneous Signals (cont.)
DDR2_DIMM5_CNTL_PAR AB8 DDR2_DIMM2_SA2 N24
DDR2_DIMM5_CNTL_PAR_ERR AM12 DDR2_DIMM3_SA0 P27
DDR2_DIMM5_NC_019 AC9 DDR2_DIMM3_SA1 P26
DDR2_DIMM5_NC_102 AL11 DDR2_DIMM3_SA2 N28
DDR2_DIMM_SCL W31 DDR2_DIMM4_SA0 K27
DDR2_DIMM_SDA Y31 DDR2_DIMM4_SA1 L28
DDR2_DIMM1_SA0 T24 DDR2_DIMM4_SA2 K28
DDR2_DIMM1_SA1 R24 DDR2_DIMM5_SA0 E26
DDR2_DIMM1_SA2 N25 DDR2_DIMM5_SA1 F28
DDR2_DIMM2_SA0 P25 DDR2_DIMM5_SA2 E28
DDR2_DIMM2_SA1 P24
FPGA #2 Clock and Reset Signals
CLK_TO_FPGA2_MGT_N H3 EXT_CLK_TO_FPGA2_N AG13
CLK_TO_FPGA2_MGT_P H4 EXT_CLK_TO_FPGA2_P AH12
DIRECT_CLK_TO_FPGA2_N AH22 FPGA2_LOW_FREQ_CLK AH20
DIRECT_CLK_TO_FPGA2_P AG22 FPGA2_RESET_N_IN AH14
FPGA #2 MII Link Interface
FPGA1_TO_FPGA2_MII_TX_CLK AE14 FPGA1_TO_FPGA2_MII_TX_DATA3 AF20
FPGA1_TO_FPGA2_MII_TX_DATA0 AE16 FPGA1_TO_FPGA2_MII_TX_EN AD20
FPGA1_TO_FPGA2_MII_TX_DATA1 AF15 FPGA1_TO_FPGA2_MII_TX_ERR AE21
FPGA1_TO_FPGA2_MII_TX_DATA2 AF21 FPGA1_TO_FPGA2_MII_TX_SPARE AF14
FPGA #2 Configuration Signals
FPGA_INIT N14 FPGA2_D_IN P15
FPGA_PROGB M22 FPGA2_DONE M15
FPGA_TMS AC14 FPGA2_DOUT_B AD15
FPGA_VBATT L23 FPGA2_HSWAPEN M23
FPGA2_CCLK N15 FPGA2_TCK AB15
FPGA2_CNFG_M0 AD21 FPGA2_TDI_IN AC15
FPGA2_CNFG_M1 AC22 FPGA2_TDO AD14
FPGA2_CNFG_M2 AD22
Table A-2: FPGA #2 Pinout (Continued)
Signal Name Pin Signal Name Pin