Xilinx Virtex-5 FPGA ML561 - Manual (Page 122)

122 www.xilinx.com Virtex-5 FPGA ML561 User Guide
UG199 (v1.2.1) June 15, 2009
Appendix C: LCD Interface R
Figure C-3 shows only the signals of interest for the LCD controller. The data sheet from
the Samsung web pages provides a complete signal listing.
Figure C-4 shows the dimensions for the 64128EFCBC-XLP LCD panel.
Figure C-3: 64128EFCBC-XLP Block Diagram
Controller
K
S
0713
LCD Panel
LED Backlight
C64
S128
Jumper J3
Parallel or Serial Selection.
Default is Parallel.
UG199_C_03_050106
1 VSS
2 VDD
3 MI
4 DB7
5 DB6
6 DB5
7 DB4
8 DB3
9 DB2
10 DB1
11 DB0
12 E
13 R/W
14 RS
15 RST
16 CS1B
17 LED+
18 LED-
Figure C-4: 64128EFCBC-XLP Dimensions
128 x 64 DOTS
56.00
2.50
2.54
69.00
74.00
UG199_C_04_050106
36.70 41.70
1 2
30 1
17 18
LED
J1
J2
8.00 Max Dimensions in mm