Xilinx Virtex-5 FPGA ML561 - Manual (Page 124)

124 www.xilinx.com Virtex-5 FPGA ML561 User Guide
UG199 (v1.2.1) June 15, 2009
Appendix C: LCD Interface R
0 0 1 0
DB0
Page 2
10H
DB1 11H
DB2 12H
DB3 13H
DB4 14H
DB5 15H
DB6 16H
DB7 17H
0 0 1 1
DB0
Page 3
18H
DB1 19H
DB2 1AH
DB3 1BH
DB4 1CH
DB5 1DH
DB6 1EH
DB7 1FH
0 1 0 0
DB0
Page 4
20H
DB1 21H
DB2 22H
DB3 23H
DB4 24H
DB5 25H
DB6 26H
DB7 27H
0 1 0 1
DB0
Page 5
28H
DB1 29H
DB2 2AH
DB3 2BH
DB4 2CH
DB5 2DH
DB6 2EH
DB7 2FH
Table C-2: LCD Panel (Continued)
DB3 DB2 DB1 DB0 Data
Line
Address