Xilinx Virtex-5 FPGA ML561 - Manual (Page 113)

Virtex-5 FPGA ML561 User Guide www.xilinx.com 113
UG199 (v1.2.1) June 15, 2009
FPGA #3 Pinout R
RLDRAM II Memory Interface (cont.)
RLD2_DQ_BY3_B4 M7 RLD2_DQ_BY3_B7 M5
RLD2_DQ_BY3_B5 N7 RLD2_DQ_BY3_B8 M6
RLD2_DQ_BY3_B6 N8
FPGA #3 Clock and Reset Signals
CLK_TO_FPGA3_MGT_N D4 EXT_CLK_TO_FPGA3_N AG13
CLK_TO_FPGA3_MGT_P E4 EXT_CLK_TO_FPGA3_P AH12
DIRECT_CLK_TO_FPGA3_N AH22 FPGA3_LOW_FREQ_CLK AH20
DIRECT_CLK_TO_FPGA3_P AG22 FPGA3_RESET_N_IN AH14
FPGA #3 MII Link Interface
FPGA1_TO_FPGA3_MII_TX_CLK AE14 FPGA1_TO_FPGA3_MII_TX_DATA3 AF20
FPGA1_TO_FPGA3_MII_TX_DATA0 AE16 FPGA1_TO_FPGA3_MII_TX_EN AD20
FPGA1_TO_FPGA3_MII_TX_DATA1 AF15 FPGA1_TO_FPGA3_MII_TX_ERR AE21
FPGA1_TO_FPGA3_MII_TX_DATA2 AF21 FPGA1_TO_FPGA3_MII_TX_SPARE AF14
FPGA #3 Configuration Signals
FPGA_INIT N14 FPGA3_D_IN P15
FPGA_PROGB M22 FPGA3_DONE M15
FPGA_TMS AC14 FPGA3_DOUT_B AD15
FPGA_VBATT L23 FPGA3_HSWAPEN M23
FPGA3_CCLK N15 FPGA3_TCK AB15
FPGA3_CNFG_M0 AD21 FPGA3_TDI_IN AC15
FPGA3_CNFG_M1 AC22 FPGA3_TDO AD14
FPGA3_CNFG_M2 AD22
FPGA #3 Test and Debug Signals
FPGA3_DIP0 AG18 FPGA3_TEST_HDR_BY0_B3 AF13
FPGA3_DIP1 AG15 FPGA3_TEST_HDR_BY0_B4 AG23
FPGA3_DIP2 AH15 FPGA3_TEST_HDR_BY0_B5 AF23
FPGA3_DIP3 AG20 FPGA3_TEST_HDR_BY0_B6 AE12
FPGA3_SPYHOLE_BK12 R8 FPGA3_TEST_HDR_BY0_B7 AE13
FPGA3_SPYHOLE_BK13 AG32 FPGA3_TEST_HDR_BY1_B0 AE24
FPGA3_TEST_HDR_BY0_B0 AE23 FPGA3_TEST_HDR_BY1_B1 AD24
FPGA3_TEST_HDR_BY0_B1 AE22 FPGA3_TEST_HDR_BY1_B2 AD25
FPGA3_TEST_HDR_BY0_B2 AG12 FPGA3_TEST_HDR_BY1_B3 AD26
Table A-3: FPGA #3 Pinout (Continued)
Signal Name Pin Signal Name Pin