Xilinx ML510 - Manual (Page 7)

ML510 Dual Processor Hardware
• The ML510 Dual Processor
design hardware includes:
• PPC440_0:
– DDR2 Interface (512 MB)
– BRAM (64 KB)
– External Memory Controller
– Networking
– UART
– Interrupt Controller
– GPIO
– EEPROM (IIC and SPI)
– System ACE CF Interface
– PLB Arbiter
• PPC440_1:
– DDR2 Interface (512 MB)
– BRAM (64 KB)
– Networking
– UART
– Interrupt Controller
– PLB Arbiter
Note: Presentation applies to the ML510