Rainbow Electronics MAX7470 - Manual (Page 7)

MAX7469/MAX7470
Detailed Description
The MAX7469/MAX7470 are complete video anti-alias-
ing solutions, ideal for fixed-pixel HDTV display tech-
nologies, such as plasma and LCD, which digitize the
input video signal and then scale the resolution to
match the native pixel format of the display. With a soft-
ware-selectable corner frequency ranging from 5MHz
to 34MHz, the MAX7469/MAX7470 support both SD
and HD video signals, including 1080i, 720p, 720i,
480p, and 480i. Higher bandwidth computer resolution
signals are also supported.
Integrated lowpass filters limit the analog video input
bandwidth for anti-aliasing and out-of-band noise
reduction prior to sampling by an ADC or video
decoder. By allowing the corner frequency to be adjust-
ed from below SD resolution to beyond HD resolutions
in 256 linear steps, the filter’s corner frequency can be
optimized dynamically for a specific input video signal
and the sampling frequency of the ADC or video
decoder. For applications requiring a passband greater
than the maximum frequency setting, a filter bypass
mode is also provided.
An I 2 C interface allows a microcontroller (µC) to config-
ure the MAX7469/MAX7470s’ performance and func-
tionality, including the clamp voltage, the filter corner
frequency, the sync source (internal/external), filter
bypassing, etc.
The Typical Operating Circuit shows the MAX7469/
MAX7470 block diagram and typical external connections.
Sync Detector and Clamp Settings
The MAX7469/MAX7470 use a video clamp circuit to
establish a DC offset for the incoming video signal after
the AC-coupling capacitor. This video clamp sets the DC
bias level of the circuit at the optimum operating point.
The MAX7469/MAX7470 support both internal and
external sync detection. Selection of internal vs. external
detection is achieved by programming the command
byte (see Table 3). After extracting the sync information
from channel 1 (or an external sync: SYNCA, SYNCB, or
SYNC), the MAX7469/MAX7470 clamp the video signal
during the sync tip portion of the video. Select one of
two possible clamp levels according to the input signal
format. Use the low level when the input signal contains
sync information, such as a Y (luma) or CVBS signal.
Pin Description
PIN NAME FUNCTION
1 DGND Digital Ground. See the Power-Supply Bypassing and Layout Considerations section.
2 EXTSYNC E xter nal S ync Inp ut. E X TS Y N C has an i nter nal 3M Ω r esi stor to g r ound . C onnect to g r ound i f not used .
3 SCL I 2 C-Compatible Serial-Clock Input
4 SDA I 2 C-Compatible Serial-Data Input/Output
5 DV DD
Digital Power Supply. Bypass to DGND with a 0.1µF capacitor. See the Power-Supply Bypassing and
Layout Considerations section.
6 OUT3 Video Output 3. OUT3 can be either DC- or AC-coupled.
7, 9, 11 AV DD
Analog Power Supply. Bypass to GND with a 0.1µF capacitor. See the Power-Supply Bypassing and
Layout Considerations section.
8 OUT2 Video Output 2. OUT2 can be either DC- or AC-coupled.
10 OUT1 Video Output 1. OUT1 can be either DC- or AC-coupled.
12 A0 I 2 C Device Address Bit 0
13 A1 I 2 C Device Address Bit 1
14, 15, 17, 19 GND
Ground. Connect all GND pins to the ground plane. See the Power-Supply Bypassing and Layout
Considerations section.
16 IN1 Video Input 1. AC-couple IN1 with a series 0.1µF capacitor.
18 IN2 Video Input 2. AC-couple IN2 with a series 0.1µF capacitor.
20 IN3 Video Input 3. AC-couple IN3 with a series 0.1µF capacitor.
— EP
E xp osed P ad . Inter nal l y connected to GN D . D o not r oute any P C b oar d tr aces und er p ackag e. C onnect
E P to the g r ound p l ane. S ee the P ow er - S up p l y Byp assi ng and Layout C onsi d er ati ons secti on.
HDTV Continuously Variable
Anti-Aliasing Filters
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