Rainbow Electronics W90N745CDG User Manual
Page 48
W90N745CD/W90N745CDG
Publication Release Date: September 22, 2006
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43
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Revision
A2
Arbitration Control Register (ARBCON)
REGISTER ADDRESS
R/W
DESCRIPTION
RESET
VALUE
ARBCON 0xFFF0_0004 R/W Arbitration Control Register
0x0000_0000
31
30
29
28
27
26
25
24
RESERVED
23
22
21
20
19
18
17
16
RESERVED
15
14
13
12
11
10
9
8
RESERVED
7
6
5
4
3
2
1
0
RESERVED IPACT
IPEN
PRTMOD
BITS
DESCRIPTION
[31:3] RESERVED
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[2] IPACT
Interrupt priority active.
When IPEN=”1”, this bit will be set when the ARM core has an
unmasked interrupt request. This bit is available only when the
PRTMOD=0.
[1] IPEN
Interrupt priority enable bit
0 = the ARM core has the lowest priority.
1 = enable to raise the ARM core priority to second
This bit is available only when the PRTMOD=0.
[0] PRTMOD
Priority mode select
0 = Fixed Priority Mode (default)
1 = Rotate Priority Mode