Rainbow Electronics W90N745CDG - Manual (Page 50)

W90N745CD/W90N745CDG
Publication Release Date: September 22, 2006
- 45 - Revision A2
Input Divider
(NR)
PFD
Feedback
Divider
(NF)
Charge
Pump
VCO
Output
Divider
(NO)
Clock
Divider
&
Selector
EXTAL
ECLKS
OTDV[1:0] CLKS[2:0]
1
0
PLL
Internal
System
Clock
INDV[4:0]
FBDV[8:0]
48MHz
Gen
480MHz
0
1
USBCKS
USB
Module
FIN
FOUT
GP0
Figure 6.2.10 System PLL block diagram
The formula of output clock of PLL is:
F
OUT
= F
IN
NO NR
NF 1
∗ ∗
F
OUT： Output clock of Output Divider
F
IN： External clock into the Input Divider
NR：Input divider value (NR = INDV + 2)
NF：Feedback divider value (NF = FBDV + 2)
NO：Output divider value (NO = OTDV)