Rainbow Electronics W90N745CDG - Manual (Page 62)

W90N745CD/W90N745CDG
Publication Release Date: September 22, 2006
- 57 - Revision A2
6.3.2.1. SDRAM Components Supported
Table 6.3.1 SDRAM supported by W90N745
SIZE TYPE BANKS ROW ADDRESSING COLUMN ADDRESSING
2Mx8 2 RA0~RA10 CA0~CA8
16M bits
1Mx16 2 RA0~RA10 CA0~CA7
8Mx8 4 RA0~RA11 CA0~CA8
64M bits
4Mx16 4 RA0~RA11 CA0~CA7
16Mx8 4 RA0~RA11 CA0~CA9
128M bits
8Mx16 4 RA0~RA11 CA0~CA8
32Mx8 4 RA0~RA12 CA0~CA9
256M bits
16Mx16 4 RA0~RA12 CA0~CA8
AHB Bus Address Mapping to SDRAM Bus
Note: * indicates the signal is not used; ** indicates the signal is fixed at logic 0 and is not used;
The HADDR prefixes have been omitted on the following tables.
A14 ~ A0 are the Address pins of the W90N745 EBI interface;
A14 and A13 are the Bank Select Signals of SDRAM.