Rainbow Electronics MAX11043 - Manual (Page 25)

MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
______________________________________________________________________________________ 25
Flash Data In Register (1Ah)
Write allowed only if flash busy bit is zero.
This is a 16-bit register that contains the data for a flash
write operation. Default = 0.
Flash Data Out Register (1Bh)
This is a read-only register. Data is valid only if flash
busy is zero.
This is a 16-bit register that contains the data for a flash
read operation.
Flash and C-RAM Register Map
The flash memory consists of 2048 words by 16 bits.
The 3 MSBs of the flash address select one of eight
pages of 256 words each. Page zero contains the
default filter coefficients for channels A and B. Page
one contains the default filter coefficients for channels
C and D. Use pages two and three for the coefficients
of custom filters. When the first word on page two con-
tains a nonzero value, the MAX11043 loads these
pages into C-RAM at power-up instead of the default
values from pages zero and one. Flash pages zero and
one include trim data. Unique trim data optimizes the
performance of each MAX11043. To maintain optimum
performance when using custom filters, copy the trim
data from flash pages zero and one to the correspond-
ing locations in flash pages two and three or to C-RAM
when writing directly to C-RAM.
Further optimization of the MAX11043 is achieved
through stage one filter coefficients for each channel.
When using custom filters, copy stage one coefficients
from pages zero and one to the corresponding loca-
tions in flash pages two and three or to C-RAM when
writing directly to C-RAM. Table 2 identifies the default
stage one filters (EQ and LP) for the MAX11043. For
custom filters, use stages two through seven first, and
only change the stage one coefficients when all seven
stages require customization.
The flash addresses below are for channel A; for chan-
nel B add 80h, for channel C add 100h, and for channel
D add 180h. To write to pages two and three of flash,
add 200h to the above values.
To load the coefficients directly to C-RAM, create a 32-
bit data word by concatenating the data in adjacent
flash locations as shown in Table 3. The C-RAM
addresses below are for channel A; for channel B add
40h, for channel C add 80h, and for channel D add
C0h.
Multiple addresses exist for some stage 1 filter coeffi-
cients as shown in Table 3. The address accessed by
the filter depends on the configuration bits as shown in
Table 2.
FILTER FIRST STAGE EQ PGAPD MODG PGAG
EQ filter stage 1 (C-RAM address 03h–05h) 1 0 XX X
LP filter for ADC gain of 1, 2, and 4; stage 1 (C-RAM address 1Dh–1Fh) X 1 XX X
LP filter for ADC gain of 8; stage 1 (C-RAM address 3Dh–3Fh) 0 0 00 0
LP filter for ADC gain of 16; stage 1 (C-RAM address 23h–25h) 0 0 XX 1
Table 2. Stage One Filter Selection
C-RAM
ADDRESS
FLASH
ADDRESS
MSB FOR C-RAM LSB FOR C-RAM
00h — Not used
00h
01h* EQ gain trim for gain = 1 —
02h — Not used
01h
03h User trim for EQ gain, default = 2000h —
04h — Not used
02h
05h Not used —
06h* — EQ filter gain for filter stage 1
03h
07h* EQ filter coefficient A2 for filter stage 1 —
Table 3. C-RAM and Flash Memory Map