Rainbow Electronics MAX9218 - Manual (Page 12)

MAX9218
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
12 ______________________________________________________________________________________
Input Frequency Detection
A frequency-detection circuit detects when the LVDS
input is not switching. When not switching, all outputs
except LOCK are low, LOCK is high, and PCLK_OUT
follows REFCLK. This condition occurs, for example, if
the serializer is not driving the interconnect or if the
interconnect is open.
Frequency Range Setting (RNG[1:0])
The RNG[1:0] inputs select the operating frequency
range of the MAX9218 and the transition time of the
outputs. Select the frequency range that includes the
MAX9217 serializer PCLK_IN frequency. Table 3 shows
the selectable frequency ranges and the correspond-
ing data rates and output transition times.
Power Down
Driving PWRDWN low puts the outputs in high imped-
ance and stops the PLL. With PWRDWN
≤ 0.3V and all
LVTTL/LVCMOS inputs ≤ 0.3V or ≥ V
CC - 0.3V, the sup-
ply current is reduced to less than 50µA. Driving
PWRDWN high initiates lock to the local reference clock
(REFCLK) and afterwards to the serial input.
Lock and Loss of Lock (
LOCK
)
When PWRDWN is driven high, the PLL begins locking
to REFCLK, drives LOCK from high impedance to high
and the other outputs from high impedance to low
except PCLK_OUT. PCLK_OUT outputs REFCLK while
the PLL is locking to REFCLK. Locking to REFCLK
takes a maximum of 16,385 REFCLK cycles. When
locking to REFCLK is complete, the serial input is moni-
tored for a transition word. When a transition word is
found, LOCK is driven low indicating valid output data,
and the parallel rate clock recovered from the serial
input is output on PCLK_OUT. PCLK_OUT is stretched
on the change from REFCLK to recovered clock (or
vice versa).
If a transition word is not detected within 2 20 cycles of
PCLK_OUT, LOCK is driven high and the other outputs
except PCLK_OUT are driven low. REFCLK is output on
PCLK_OUT and the deserializer continues monitoring
the serial input for a transition word. See Figure 7 for
the synchronization timing diagram.
Output Enable (OUTEN) and
Busing Outputs
The outputs of two MAX9218s can be bused to form a
2:1 mux with the outputs controlled by the output
enable. Wait 30ns between disabling one deserializer
(driving OUTEN low) and enabling the second one (dri-
ving OUTEN high) to avoid contention of the bused out-
puts. OUTEN controls all outputs.
Rising or Falling Output Latch Edge (R/
F
)
The MAX9218 has a selectable rising or falling output
latch edge through a logic setting on R/F. Driving R/F
high selects the rising output latch edge, which latches
the parallel output data into the next chip on the rising
edge of PCLK_OUT. Driving R/F low selects the falling
output latch edge, which latches the parallel output
data into the next chip on the falling edge of
PCLK_OUT. The MAX9218 output-latch-edge polarity
does not need to match the MAX9217 serializer input-
latch-edge polarity. Select the latch-edge polarity
required by the chip being driven by the MAX9218.
AC-COUPLING CAPACITOR VALUE
vs. PARALLEL CLOCK FREQUENCY
PARALLEL CLOCK FREQUENCY (MHz)
CAPACITOR VALUE (nF)
33 30 21 24 27
35
50
65
80
95
110
125
140
20
18 36
TWO CAPACITORS PER LINK
FOUR CAPACITORS PER LINK
RNG1 RNG0
PARALLEL
CLOCK
(MHz)
SERIAL
DATA RATE
(Mbps)
OUTPUT
TRANSITION
TIME
0 0
0 1
3 to 7 60 to 140
1 0 7 to 15 140 to 300
Slow
1 1 15 to 35 300 to 700 Fast
Figure 12. AC-Coupling Capacitor Values vs. Clock Frequency
of 18MHz to 35MHz
Table 3. Frequency Range Programming