Rainbow Electronics MAX9218 - Manual (Page 7)

MAX9218
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
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Functional Diagram
IN+
IN-
RNG0
RNG1
MAX9218
SER-TO-PAR
TIMING AND
CONTROL
PLL
DC BALANCE/
DECODE
1
0
R/F
OUTEN
RGB_OUT[17:0]
LOCK
PWRDWN
REFCLK
PCLK_OUT
DE_OUT
CNTL_OUT[8:0]
LVDS
RECEIVER 1.2V
IN+
R IB
R
IB
IN-
Figure 1. LVDS Input Bias
PCLK_OUT
ODD
RGB_OUT
CNTL_OUT
EVEN
RGB_OUT
CNTL_OUT
RISING LATCH EDGE SHOWN (R/F = HIGH).
Figure 2. Worst-Case Output Pattern
DE_OUT
LOCK
PCLK_OUT
RGB_OUT[17:0]
CNTL_OUT[8:0]
0.9V CCO
0.1V CCO
t F t R
Figure 3. Output Rise and Fall Times
PCLK_OUT
t LOW
t HIGH
2.0V
0.8V
Figure 4. High and Low Times