Rainbow Electronics ATmega162V - Manual (Page 267)

267
ATmega162/V
2513E–AVR–09/03
SPI Timing
Characteristics See Figure 116 and Figure 117 for details.
Note: 1. In SPI Programming mode, the minimum SCK high/low period is:
– 2 t
CLCL
for f
CK
< 12 MHz
– 3 t
CLCL
for f
CK
> 12 MHz.
Figure 116. SPI Interface Timing Requirements (Master Mode)
Table 114. SPI Timing Parameters
Description Mode Min Typ Max
1 SCK period Master See Table 68
ns
2 SCK high/low Master 50% duty cycle
3 Rise/Fall time Master 3.6
4 Setup Master 10
5 Hold Master 10
6 Out to SCK Master 0.5 • t
sck
7 SCK to out Master 10
8 SCK to out high Master 10
9 SS low to out Slave 15
10 SCK period Slave 4 • t
ck
11 SCK high/low (1) Slave 2 • t
ck
12 Rise/Fall time Slave 1.6 µs
13 Setup Slave 10
ns
14 Hold Slave t
ck
15 SCK to out Slave 15
16 SCK to SS high Slave 20
17 SS high to tri-state Slave 10
18 SS low to SCK Slave 2 • t
ck
MOSI
(Data Output)
SCK
(CPOL = 1)
MISO
(Data Input)
SCK
(CPOL = 0)
SS
MSB LSB
LSB MSB
...
...
6 1
2 2
3 4 5
8 7