Rainbow Electronics DS2172 - Manual (Page 4)

DS2172
031197 4/20
DETAILED PIN DESCRIPTION Table 1
PIN SYMBOL TYPE DESCRIPTION
1 TL I Transmit Load. A positive–going edge loads the pattern generator with the
contents of the Pattern Set Registers. The MSB of the repetitive or pseudo-
random pattern appears at TDATA after the third positive edge of TCLK from
asserting TL. TL is logically OR’ed with PCR.7 and should be tied to V
SS
if
not used. See Figure 8 for timing information.
2 AD0 I/O Data Bus. A 8–bit multiplexed address/data bus.
3 AD1 I/O Data Bus. A 8–bit multiplexed address/data bus.
4 TEST I Test. Set high to 3–state all output pins (INT, ADx, TDATA, RLOS). Should
be tied to V
SS
to enable all outputs.
5 V
SS
– Signal Ground. 0.0 volts. Should be tied to local ground plane.
6 AD2 I/O Data Bus. A 8–bit multiplexed address/data bus.
7 AD3 I/O Data Bus. A 8–bit multiplexed address/data bus.
8 AD4 I/O Data Bus. A 8–bit multiplexed address/data bus.
9 AD5 I/O Data Bus. A 8–bit multiplexed address/data bus.
10 AD6 I/O Data Bus. A 8–bit multiplexed address/data bus.
11 AD7 I/O Data Bus. A 8–bit multiplexed address/data bus.
12 V
SS
– Signal Ground. 0.0 volts. Should be tied to local ground plane.
13 V
DD
– Positive Supply. 5.0 volts.
14 BTS I Bus Type Select. Strap high to select Motorola bus timing; strap low to select
Intel bus timing. This pin controls the function of the RD(DS), ALE(AS), and
WR(R/W) pins. If BTS = 1, then these pins assume the function listed in
parenthesis ().
15 RD (DS) I Read Input (Data Strobe).
16 CS I Chip Select. Must be low to read or write the port.
17 ALE (AS) I Address Latch Enable (Address Strobe). A positive going edge serves to
demultiplex the bus.
18 WR (R/W) I Write Input (Read/Write).
19 INT O Alarm Interrupt. Flags host controller during conditions defined in Status
Register. Active low, open drain output.
20 V
DD
– Positive Supply. 5.0 volts.
21 V
SS
– Signal Ground. 0.0 volts. Should be tied to local ground plane.
22 LC I Load Count. A positive–going edge latches the current bit and bit error count
into the user accessible BCR and BECR registers and clears the internal
count registers. LC is logically OR’ed with control bit PCR.4. Should be tied
to V
SS
if not used.
23 RLOS O Receive Loss Of Sync. Indicates the real time status of the receive synchro-
nizer. Active high output; transitions low after receiving 32 matching bits.