Rainbow Electronics MAX1471 - Manual (Page 16)

MAX1471
Serial Control Interface
Communication Protocol
The MAX1471 can use a 4-wire interface or a 3-wire
interface (default). In both cases, the data input must
follow the timing diagrams shown in Figures 8 and 9.
Note that the DIO line must be held LOW while CS is
high. This is to prevent the MAX1471 from entering dis-
continuous receive mode if the DRX bit is high. The
data is latched on the rising edge of SCLK, and there-
fore must be stable before that edge. The data
sequencing is MSB first, the command (C[3:0]; see
Table 3), the register address (A[3:0]; see Table 4) and
the data (D[7:0]; see Table 5).
The mode of operation (3-wire or 4-wire interface) is
selected by DOUT_FSK and/or DOUT_ASK bits in the
configuration register. Either of those bits selects the
ASKOUT and/or FSKOUT line as a SERIAL data output.
Upon receiving a read register command (0x2), the
serial interface outputs the data on either pin, accord-
ing to Figure 10.
If neither of these bits are 1, the 3-wire interface is
selected (default on power-up) and the DIO line is
effectively a bidirectional input/output line. DIO is
selected as an output of the MAX1471 for the following
CS cycle whenever a READ command is received. The
CPU must tri-state the DIO line on the cycle of CS that
follows a read command, so the MAX1471 can drive
the data output line. Figure 11 shows the diagram of
the 3-wire interface. Note that the user can choose to
send either 16 cycles of SCLK, as in the case of the 4-
wire interface, or just eight cycles, as all the registers
are 8-bits wide. The user must drive DIO low at the end
of the read sequence.
The MASTER RESET command (0x3) (see Table 3)
sends a reset signal to all the internal registers of the
MAX1471 just like a power-off and power-on sequence
would do. The reset signal remains active for as long as
CS is high after the command is sent.
Continuous Receive Mode (DRX = 0)
In continuous receive mode, individual analog modules
can be powered on directly through the power configu-
ration register (register 0x0). The SLEEP bit (bit 0)
overrides the power settings of the remaining bits and
puts the part into deep-sleep mode when set. It is also
necessary to write the frequency divisor of the external
crystal in the oscillator frequency register (register 0x3)
to optimize image rejection and to enable accurate cali-
bration sequences for the polling timer and the FSK
demodulator. This number is the integer result of f
XTAL /
100kHz.
If the FSK receive function is selected, it is necessary to
perform an FSK calibration to improve receive sensitivi-
ty. Polling timer calibration is not necessary. See the
Calibration section for more information.
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
16 ______________________________________________________________________________________
Figure 7. Fast Receiver Recovery in FSK Mode Utilizing Peak
Detectors
200mV/div
DATA OUTPUT
2V/div
MIN PEAK DETECTOR
MAX PEAK DETECTOR
RECEIVER ENABLED, TRK_EN SET
TRK_EN CLEARED
FILTER OUTPUT
DATA OUTPUT
100 µs/div
Figure 8. Digital Communications Timing Diagram
t DH
HIGH-IMPEDANCE
DATA OUT DATA IN
HIGH-IMPEDANCE HI-Z
SCLK
DIO D7 D0
CS
t CSS t CH
t DI
t SC t CL
t DV
t CSH
t DO
t TR
t CS t CSI