Document Outline

• List of Figures
• List of Tables
• Overview
  • 1.1 General Description
  • 1.2 Features
• Architecture Overview
  • 2.1 CPU Core
    • 2.1.1 Integer Unit
    • 2.1.2 Memory Management Unit
    • 2.1.3 Cache and TLB Subsystem
    • 2.1.4 Bus Controller Unit
    • 2.1.5 Floating Point Unit
  • 2.2 GeodeLink™ Control Processor
  • 2.3 GeodeLink™ Interface Units
  • 2.4 GeodeLink™ Memory Controller
  • 2.5 Graphics Processor
  • 2.6 Display Controller
  • 2.7 Video Processor
    • 2.7.1 CRT Interface
    • 2.7.2 TFT Controller
    • 2.7.3 Video Output Port
  • 2.8 Video Input Port
  • 2.9 GeodeLink™ PCI Bridge
  • 2.10 Security Block
• Signal Definitions
  • 3.1 Buffer Types
  • 3.2 Bootstrap Options
  • 3.3 Ball Assignments
  • 3.4 Signal Descriptions
    • 3.4.1 System Interface Signals
    • 3.4.2 PLL Interface Signals
    • 3.4.3 Memory Interface Signals (DDR)
    • 3.4.4 Internal Test and Measurement Interface Signals
    • 3.4.5 PCI Interface Signals
    • 3.4.6 TFT Display Interface Signals
    • 3.4.7 CRT Display Interface Signals
    • 3.4.8 VIP Interface Signals
    • 3.4.9 Power and Ground Interface Signals
• GeodeLink™ Interface Unit
  • 4.1 MSR Set
    • 4.1.1 Port Address
    • 4.1.2 Port Addressing Exceptions
    • 4.1.3 Memory and I/O Mapping
      • 4.1.3.1 Memory Routing and Translation
      • 4.1.3.2 I/O Routing and Translation
      • 4.1.3.3 Special Cycles
  • 4.2 GLIU Register Descriptions
    • 4.2.1 Standard GeodeLink™ Device (GLD) MSRs
      • 4.2.1.1 GLD Capabilities MSR (GLD_MSR_CAP)
      • 4.2.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG)
      • 4.2.1.3 GLD SMI MSR (GLD_MSR_SMI)
      • 4.2.1.4 GLD Error MSR (GLD_MSR_ERROR)
      • 4.2.1.5 GLD Power Management MSR (GLD_MSR_PM)
      • 4.2.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG)
    • 4.2.2 GLIU Specific Registers
      • 4.2.2.1 Coherency (COH)
      • 4.2.2.2 Port Active Enable (PAE)
      • 4.2.2.3 Arbitration (ARB)
      • 4.2.2.4 Asynchronous SMI (ASMI)
      • 4.2.2.5 Asynchronous ERR (AERR)
      • 4.2.2.6 GLIU Physical Capabilities (PHY_CAP)
      • 4.2.2.7 N Outstanding Response (NOUT_RESP)
      • 4.2.2.8 N Outstanding Write Data (NOUT_WDATA)
      • 4.2.2.9 SLAVE_ONLY
      • 4.2.2.10 WHO AM I (WHOAMI)
      • 4.2.2.11 GLIU Slave Disable (GLIU_SLV)
      • 4.2.2.12 Arbitration2 (ARB2)
    • 4.2.3 GLIU Statistic and Comparator MSRs
      • 4.2.3.1 Descriptor Statistic Counter (STATISTIC_CNT[0:3])
      • 4.2.3.2 Statistic Mask (STATISTIC_MASK[0:3]
      • 4.2.3.3 Statistic Action (STATISTIC_ACTION[0:3]
      • 4.2.3.4 Request Compare Value (RQ_COMPARE_VAL[0:3]
      • 4.2.3.5 Request Compare Mask (RQ_COMPARE_MASK[0:3]
      • 4.2.3.6 DA Compare Value Low (DA_COMPARE_VAL_LO[0:3]
      • 4.2.3.7 DA Compare Value High (DA_COMPARE_VAL_HI[0:3]
      • 4.2.3.8 DA Compare Mask Low (DA_COMPARE_MASK_LO[0:3])
      • 4.2.3.9 DA Compare Mask High (DA_COMPARE_MASK_HI[0:3])
    • 4.2.4 P2D Descriptor Registers
      • 4.2.4.1 P2D Base Mask Descriptor (P2D_BM)
      • 4.2.4.2 P2D Base Mask Offset Descriptor (P2D_BMO)
      • 4.2.4.3 P2D Range Descriptor (P2D_R)
      • 4.2.4.4 P2D Range Offset Descriptor (P2D_RO)
      • 4.2.4.5 P2D Swiss Cheese Descriptor (P2D_SC)
    • 4.2.5 SPARE MSRs (SPARE_MSR[0:9], A:F)
    • 4.2.6 I/O Descriptors
      • 4.2.6.1 IOD Base Mask Descriptors (IOD_BM)
      • 4.2.6.2 IOD Swiss Cheese Descriptors (IOD_SC)
• CPU Core
  • 5.1 Core Processor Initialization
  • 5.2 Instruction Set Overview
    • 5.2.1 Lock Prefix
    • 5.2.2 Register Sets
  • 5.3 Application Register Set
    • 5.3.1 General Purpose Registers
    • 5.3.2 Segment Registers
    • 5.3.3 Instruction Pointer Register
    • 5.3.4 EFLAGS Register
  • 5.4 System Register Set
    • 5.4.1 Control Registers
  • 5.5 CPU Core Register Descriptions
    • 5.5.1 Standard GeodeLink™ Device MSRs
      • 5.5.1.1 GLD Capabilities MSR (GLD_MSR_CAP)
      • 5.5.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG)
      • 5.5.1.3 GLD SMI MSR (GLD_MSR_SMI)
      • 5.5.1.4 GLD Error MSR (GLD_MSR_ERROR)
      • 5.5.1.5 GLD Power Management MSR (GLD_MSR_PM)
      • 5.5.1.6 GLD Diagnostic Bus Control MSR (GLD_MSR_DIAG)
    • 5.5.2 CPU Core Specific MSRs
      • 5.5.2.1 Time Stamp Counter MSR (TSC_MSR)
      • 5.5.2.2 Performance Event Counter 0 MSR (PERF_CNT0_MSR)
      • 5.5.2.3 Performance Event Counter 1 MSR (PERF_CNT1_MSR)
      • 5.5.2.4 SYSENTER/SYSEXIT Code Segment Selector MSR (SYS_CS_MSR)
      • 5.5.2.5 SYSENTER/SYSEXIT Stack Pointer MSR (SYS_SP_MSR)
      • 5.5.2.6 SYSENTER/SYSEXIT Instruction Pointer MSR (SYS_IP_MSR)
      • 5.5.2.7 Performance Event Counter 0 Select MSR (PERF_SEL0_MSR
      • 5.5.2.8 Performance Event Counter 1 Select MSR (PERF_SEL1_MSR)
      • 5.5.2.9 Instruction Fetch Configuration MSR (IF_CONFIG_MSR)
      • 5.5.2.10 IF Invalidate MSR (IF_INVALIDATE_MSR)
      • 5.5.2.11 IF Test Address MSR (IF_TEST_ADDR_MSR)
      • 5.5.2.12 IF Test Data MSR (IF_TEST_DATA_MSR)
      • 5.5.2.13 IF Sequential Count MRS (IF_SEQCOUNT_MSR)
      • 5.5.2.14 IF Built-In Self-Test MSR (IF_BIST_MSR)
      • 5.5.2.15 Exception Unit (XC) Configuration MSR (XC_CONFIG_MSR)
      • 5.5.2.16 XC Mode MSR (XC_MODE_MSR)
      • 5.5.2.17 XC History MSR (XC_HIST_MSR)
      • 5.5.2.18 XC Microcode Address MSR (XC_UADDR_MSR)
      • 5.5.2.19 ID Configuration MSR (ID_CONFIG_MSR)
      • 5.5.2.20 SMM Control MSR (SMM_CTL_MSR)
      • 5.5.2.21 Debug Management Interrupt (DMI) Control Register
      • 5.5.2.22 Temporary MSRs
      • 5.5.2.23 Segment Selector/Flags MSRs
      • 5.5.2.24 SMM Header MSR (SMM_HDR_MSR)
      • 5.5.2.25 DMM Header MSR (DMM_HDR_MSR)
      • 5.5.2.26 Segment Base/Limit MSRs
      • 5.5.2.27 Debug Registers 1 and 0 MSR (DR1_DR0_MSR)
      • 5.5.2.28 Debug Registers 3 and 2 MSR (DR3_DR2_MSR)
      • 5.5.2.29 Debug Registers 7 and 6 MSR (DR6_DR7_MSR)
      • 5.5.2.30 Extended Debug Registers 1 and 0 MSR (XDR1_XDR0_MSR)
      • 5.5.2.31 Extended Debug Registers 3 and 2 MSR (XDR3_XDR2_MSR)
      • 5.5.2.32 Extended Debug Registers 5 and 4 MSR (XDR5_XDR4_MSR)
      • 5.5.2.33 Extended Debug Registers 7 and 6 MSR (XDR7_XDR6_MSR)
      • 5.5.2.34 Extended Debug Registers 9 and 8 MSR (XDR9_XDR8_MSR)
      • 5.5.2.35 Extended Debug Registers 11 and 10 MSR (XDR11_XDR10_MSR)
      • 5.5.2.36 EX Stage Instruction Pointer MSR (EX_IP_MSR)
      • 5.5.2.37 WB Stage Instruction Pointer MSR (WB_IP_MSR)
      • 5.5.2.38 EX Stage Linear Instruction Pointer MSR (EX_LIP_MSR)
      • 5.5.2.39 WB Stage Linear Instruction Pointer MSR (WB_LIP_MSR)
      • 5.5.2.40 C1/C0 Linear Instruction Pointer MSR (C1_C0_LIP_MSR)
      • 5.5.2.41 C3/C2 Linear Instruction Pointer MSR (C3_C2_LIP_MSR)
      • 5.5.2.42 Floating Point Environment Code Segment (FPENV_CS_MSR)
      • 5.5.2.43 Floating Point Environment Instruction Pointer (FPENV_IP_MSR)
      • 5.5.2.44 Floating Point Environment Data Segment (FPENV_DS_MSR)
      • 5.5.2.45 Floating Point Environment Data Pointer (FPENV_DP_MSR)
      • 5.5.2.46 Floating Point Environment Opcode Pointer (FPENV_OP_MSR)
      • 5.5.2.47 Address Calculation Unit Configuration MSR (AC_CONFIG_MSR)
      • 5.5.2.48 General Register MSRs
      • 5.5.2.49 Extended Flags MSR (EFLAG_MSR)
      • 5.5.2.50 Control Register 0 MSR (CR0_MSR)
      • 5.5.2.51 Instruction Memory Configuration MSR (IM_CONFIG_MSR)
      • 5.5.2.52 Instruction Cache Index MSR (IC_INDEX_MSR)
      • 5.5.2.53 Instruction Cache Data MSR (IC_DATA_MSR)
      • 5.5.2.54 Instruction Cache Tag (IC_TAG_MSR)
      • 5.5.2.55 Instruction Cache Tag with Increment (IC_TAG_I_MSR)
      • 5.5.2.56 L0 Instruction Cache Data MSR (L0_IC_DATA_MSR)
      • 5.5.2.57 L0 Instruction Cache Tag with Increment MSR (L0_IC_TAG_I_MSR)
      • 5.5.2.58 L1 Instruction TLB Index (ITB_INDEX_MSR)
      • 5.5.2.59 L1 Instruction TLB Least Recently Used MSR (ITB_LRU_MSR)
      • 5.5.2.60 L1 Instruction TLB Entry MSRs
      • 5.5.2.61 Instruction Memory Subsystem BIST Tag MSR (IM_BIST_TAG_MSR)
      • 5.5.2.62 Instruction Memory Subsystem BIST Data MSR (IM_BIST_DATA_MSR)
      • 5.5.2.63 Data Memory Subsystem Configuration 0 MSR (DM_CONFIG0_MSR)
      • 5.5.2.64 Data Memory Subsystem Configuration 1 MSR (DM_CONFIG1_MSR)
      • 5.5.2.65 Data Memory Subsystem Prefetch Lock MSR (DM_PFLOCK_MSR)
      • 5.5.2.66 Default Region Configuration Properties MSR (RCONF_DEFAULT_MSR)
      • 5.5.2.67 Region Configuration Bypass MSR (RCONF_BYPASS_MSR)
      • 5.5.2.68 Region Configuration A0000-BFFFF MSR (RCONF_A0_BF_MSR)
      • 5.5.2.69 Region Configuration C0000-DFFFF MSR (RCONF_C0_DF_MSR)
      • 5.5.2.70 Region Configuration E0000-FFFFF MSR (RCONF_E0_FF_MSR)
      • 5.5.2.71 Region Configuration SMM MSR (RCONF_SMM_MSR)
      • 5.5.2.72 Region Configuration DMM MSR (RCONF_DMM_MSR)
      • 5.5.2.73 Region Configuration Range MSRs 0 through 7
      • 5.5.2.74 x86 Control Registers MSRs (CR1, CR2, CR3, CR4)
      • 5.5.2.75 Data Cache Index MSR (DC_INDEX_MSR)
      • 5.5.2.76 Data Cache Data MSR (DC_DATA_MSR)
      • 5.5.2.77 Data Cache Tag MSR (DC_TAG_MSR)
      • 5.5.2.78 Data Cache Tag with Increment MSR (DC_TAG_I_MSR)
      • 5.5.2.79 Data/Instruction Cache Snoop Register (SNOOP_MSR)
      • 5.5.2.80 L1 Data TLB Index Register (L1DTLB_INDEX_MSR)
      • 5.5.2.81 L1 Data TLB Least Recently Used MSR (L1DTLB_LRU_MSR)
      • 5.5.2.82 L1 Data TLB Entry MSR (L1DTLB_ENTRY_MSR)
      • 5.5.2.83 L1 Data TLB Entry with Increment MSR (L1DTLB_ENTRY_I_MSR)
      • 5.5.2.84 L2 TLB/DTE/PTE Index MSR (L2TLB_INDEX_MSR)
      • 5.5.2.85 L2 TLB/DTE/PTE Least Recently Used MSR (L2TLB_LRU_MSR)
      • 5.5.2.86 L2 TLB/DTE/PTE Entry MSR (L2TLB_ENTRY_MSR)
      • 5.5.2.87 L2 TLB/DTE/PTE Entry with Increment MSR (L2TLB_ENTRY_I_MSR)
      • 5.5.2.88 Data Memory Subsystem Built-In Self-Test MSR (DM_BIST_MSR)
      • 5.5.2.89 Bus Controller Configuration 0 MSR (BC_CONFIG0_MSR)
      • 5.5.2.90 Bus Controller Configuration 1 MSR (BC_CONFIG1_MSR)
      • 5.5.2.91 Reserved Status MSR (RSVD_STS_MSR)
      • 5.5.2.92 MSR Lock MSR (MSR_LOCK_MSR)
      • 5.5.2.93 Real Time Stamp Counter MSR (RTSC_MSR)
      • 5.5.2.94 TSC and RTSC Low DWORDs MSR (RTSC_TSC_MSR)
      • 5.5.2.95 L2 Cache Configuration MSR (L2_CONFIG_MSR)
      • 5.5.2.96 L2 Cache Status MSR (L2_STATUS_MSR)
      • 5.5.2.97 L2 Cache Index MSR (L2_INDEX_MSR)
      • 5.5.2.98 L2 Cache Data MSR (L2_DATA_MSR)
      • 5.5.2.99 L2 Cache Tag MSR (L2_TAG_MSR)
      • 5.5.2.100 L2 Cache Tag with Increment MSR (L2_TAG_I_MSR)
      • 5.5.2.101 L2 Cache Built-In Self-Test MSR (L2_BIST_MSR)
      • 5.5.2.102 L2 Cache Treatment Control MSR (L2_TRTMNT_CTL_MSR)
      • 5.5.2.103 Power Mode MSR (PMODE_MSR)
      • 5.5.2.104 Bus Controller Extended Debug Registers 1 and 0 MSR (BXDR1_BXDR0_MSR)
      • 5.5.2.105 Bus Controller Extended Debug Registers 3 and 2 MSR (BXDR3_BXDR2_MSR)
      • 5.5.2.106 Bus Controller Extended Debug Registers 6 and 7 MSR (BXDR6_BXDR7_MSR)
      • 5.5.2.107 Bus Controller Debug Registers 0 through 3 MSRs
      • 5.5.2.108 Bus Controller Debug Register 6 MSR (BDR6_MSR)
      • 5.5.2.109 Bus Controller Debug Register 7 MSR (BDR7_MSR)
      • 5.5.2.110 Memory Subsystem Array Control Enable MSR (MSS_ARRAY_CTL_EN_MSR)
      • 5.5.2.111 Memory Subsystem Array Control 0 MSR (MSS_ARRAY_CTL0_MSR)
      • 5.5.2.112 Memory Subsystem Array Control 1 MSR (MSS_ARRAY_CTL1_MSR)
      • 5.5.2.113 Memory Subsystem Array Control 2 MSR (MSS_ARRAY_CTL2_MSR)
      • 5.5.2.114 FPU Modes MSR (FP_MODE_MSR)
      • 5.5.2.115 FPU Reserved MSR (FPU_RSVD_MSR)
      • 5.5.2.116 FPU Reserved MSR (FPU_RSVD_MSR)
      • 5.5.2.117 FPU x87 Control Word MSR (FPU_CW_MSR)
      • 5.5.2.118 FPU x87 Status Word MSR (FPU_SW_MSR)
      • 5.5.2.119 FPU x87 Tag Word MSR (FPU_TW_MSR)
      • 5.5.2.120 FPU Busy MSR (FPU_BUSY_MSR)
      • 5.5.2.121 FPU Register Map MSR (FPU_MAP_MSR)
      • 5.5.2.122 Mantissa of Rx MSRs
      • 5.5.2.123 Exponent of Rx MSRs
      • 5.5.2.124 FPU Reserved MSRs (FPU_RSVD_MSR)
      • 5.5.2.125 CPU ID MSRs
• Integrated Functions
  • 6.1 GeodeLink™ Memory Controller
    • 6.1.1 Functional Hardware
      • 6.1.1.1 Address Translation
      • 6.1.1.2 Arbitration
      • 6.1.1.3 Data Path
      • 6.1.1.4 GLMC/GLCP/Pad Delay Control Settings
      • 6.1.1.5 Basic Timing Diagrams
    • 6.1.2 Power Control
      • 6.1.2.1 Entry into PMode1 (Save-to-RAM)
      • 6.1.2.2 Resume from PMode1
    • 6.1.3 BIOS Initialization Sequence
  • 6.2 GeodeLink™ Memory Controller Register Descriptions
    • 6.2.1 Standard GeodeLink™ Device (GLD) MSRs
      • 6.2.1.1 GLD Capabilities MSR (GLD_MSR_CAP)
      • 6.2.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG) - Not Used
      • 6.2.1.3 GLD SMI MSR (GLD_MSR_SMI)
      • 6.2.1.4 GLD Error MSR (GLD_MSR_ERROR)
      • 6.2.1.5 GLD Power Management (GLD_MSR_PM)
      • 6.2.1.6 GLD Diagnostic (GLD_MSR_DIAG)
    • 6.2.2 GLMC Specific MSRs
      • 6.2.2.1 Row Addresses Bank0 DIMM0, Bank1 DIMM0 (MC_CF_BANK01)
      • 6.2.2.2 Row Addresses Bank2 DIMM0, Bank3 DIMM0 (MC_CF_BANK23)
      • 6.2.2.3 Row Addresses Bank4 DIMM0, Bank5 DIMM0 (MC_CF_BANK45)
      • 6.2.2.4 Row Addresses Bank6 DIMM0, Bank7 DIMM0 (MC_CF_BANK67)
      • 6.2.2.5 Row Addresses Bank0 DIMM1, Bank1 DIMM0 (MC_CF_BANK89)
      • 6.2.2.6 Row Addresses Bank2 DIMM1, Bank3 DIMM1 (MC_CF_BANKAB)
      • 6.2.2.7 Row Addresses Bank4 DIMM1, Bank5 DIMM1 (MC_CF_BANKCD)
      • 6.2.2.8 Row Addresses Bank6 DIMM1, Bank7 DIMM1 (MC_CF_BANKEF)
      • 6.2.2.9 Refresh and SDRAM Program (MC_CF07_DATA)
      • 6.2.2.10 Timing and Mode Program (MC_CF8F_DATA)
      • 6.2.2.11 Feature Enables (MC_CF1017_DATA)
      • 6.2.2.12 Performance Counters (MC_CFPERF_CNT1)
      • 6.2.2.13 Counter and CAS Control (MC_PERCNT2)
      • 6.2.2.14 Clocking and Debug (MC_CFCLK_DBUG)
      • 6.2.2.15 Page Open Status (MC_CFPG_OPEN)
      • 6.2.2.16 Reserved Register
      • 6.2.2.17 PM Sensitivity Counters (MC_CF_PMCTR)
  • 6.3 Graphics Processor
    • 6.3.1 Command Buffer
    • 6.3.2 Channel 3
      • 6.3.2.1 Rotating BLTs
      • 6.3.2.2 Rotating Video
      • 6.3.2.3 Color Depth Conversion
      • 6.3.2.4 Palletized Color Support
      • 6.3.2.5 Anti-Aliased Text Support
      • 6.3.2.6 8x8 Color Pattern
      • 6.3.2.7 Patterned Vectors
      • 6.3.2.8 Channel 3 Host Source
      • 6.3.2.9 Channel 3 Hints
    • 6.3.3 BLT Operation
    • 6.3.4 Vector Operation
    • 6.3.5 Pipelined Operation
    • 6.3.6 Pattern Generation
      • 6.3.6.1 Monochrome Patterns
      • 6.3.6.2 Color Patterns
    • 6.3.7 8x8 Color Patterns
    • 6.3.8 Source Data
      • 6.3.8.1 Source Data Formats
      • 6.3.8.2 Host Source
      • 6.3.8.3 Source Expansion
      • 6.3.8.4 Source Transparency
    • 6.3.9 Destination Data
    • 6.3.10 Raster Operations (ROP)
    • 6.3.11 Image Compositing Using Alpha
  • 6.4 Graphics Processor Register Definitions
    • 6.4.1 Standard GeodeLink™ Device (GLD) MSRs
      • 6.4.1.1 GLD Capabilities MSR (GLD_MSR_CAP)
      • 6.4.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG)
      • 6.4.1.3 GLD SMI MSR (GLD_MSR_SMI)
      • 6.4.1.4 GLD Error MSR (GLD_MSR_ERROR)
      • 6.4.1.5 GLD Power Management MSR (GLD_MSR_PM)
      • 6.4.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG)
    • 6.4.2 Graphics Processor Configuration Registers
      • 6.4.2.1 Destination Offset (GP_DST_OFFSET)
      • 6.4.2.2 Source Offset (GP_SRC_OFFSET)
      • 6.4.2.3 Vector Error (GP_VEC_ERR)
      • 6.4.2.4 Stride (GP_STRIDE)
      • 6.4.2.5 BLT Width/Height (GP_WID_HEIGHT)
      • 6.4.2.6 Vector Length (GP_VEC_LEN)
      • 6.4.2.7 Source Color Foreground (GP_SRC_COLOR_FG)
      • 6.4.2.8 Source Color Background (GP_SRC_COLOR_BG)
      • 6.4.2.9 Pattern Color (GP_PAT_COLOR_x)
      • 6.4.2.10 Pattern Data (GP_PAT_DATA_x)
      • 6.4.2.11 Raster Mode (GP_RASTER_MODE)
      • 6.4.2.12 Vector Mode (GP_VECTOR_MODE)
      • 6.4.2.13 BLT Mode (GP_BLT_MODE)
      • 6.4.2.14 Status and Reset (GP_BLT_STATUS, GP_RESET)
      • 6.4.2.15 Host Source (GP_HST_SRC)
      • 6.4.2.16 Base Offset (GP_BASE_OFFSET)
      • 6.4.2.17 Command Top (GP_CMD_TOP)
      • 6.4.2.18 Command Bottom (GP_CMD_BOT)
      • 6.4.2.19 Command Read (GP_CMD_READ)
      • 6.4.2.20 Command Write (GP_CMD_WRITE)
      • 6.4.2.21 Offset (GP_CH3_OFFSET)
      • 6.4.2.22 Stride (GP_CH3_MODE_STR)
      • 6.4.2.23 Width/Height (GP_CH3_WIDHI)
      • 6.4.2.24 Host Source (GP_CH3_HSRC)
      • 6.4.2.25 LUT Index (GP_LUT_INDEX)
      • 6.4.2.26 LUT Data (GP_LUT_DATA)
      • 6.4.2.27 Interrupt Control (GP_INT_CNTRL)
  • 6.5 Display Controller
    • 6.5.1 GUI Functional Overview
      • 6.5.1.1 Display Mode Support
      • 6.5.1.2 Display FIFO
      • 6.5.1.3 Hardware Cursor and Icon Overlays
      • 6.5.1.4 Display Refresh Compression
      • 6.5.1.5 Dirty/Valid RAM
      • 6.5.1.6 Palette/Gamma RAM
      • 6.5.1.7 Display Address Generator
      • 6.5.1.8 Display Timing Generator
      • 6.5.1.9 Video Overlay Support
      • 6.5.1.10 Output Formats
    • 6.5.2 VBI Data
    • 6.5.3 GenLock
    • 6.5.4 VGA Block Functional Overview
      • 6.5.4.1 VGA Modes
    • 6.5.5 VGA Block Operation
      • 6.5.5.1 Frame Buffer
      • 6.5.5.2 Graphics Controller
      • 6.5.5.3 Write Modes
      • 6.5.5.4 Read Modes
    • 6.5.6 Graphics Scaler/Filter
    • 6.5.7 Color Key Elimination
    • 6.5.8 Using the Graphics Filter
    • 6.5.9 Interlaced Modes
    • 6.5.10 Interlaced Timing Examples
  • 6.6 Display Controller Register Descriptions
    • 6.6.1 Standard GeodeLink™ Device (GLD) Registers (MSRs)
      • 6.6.1.1 GLD Capabilities MSR (GLD_MSR_CAP)
      • 6.6.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG)
      • 6.6.1.3 GLIU0 Device SMI MSR (GLD_MSR_SMI)
      • 6.6.1.4 GLD Error MSR (GLD_MSR_ERROR)
      • 6.6.1.5 GLD Power Management MSR (GLD_MSR_PM)
      • 6.6.1.6 GLIU0 Device Diagnostic MSR (GLD_MSR_DIAG)
    • 6.6.2 Display Controller Specific MSRs
      • 6.6.2.1 SPARE MSR
      • 6.6.2.2 DC RAM Control MSR (DC_RAM_CTL_MSR)
    • 6.6.3 Configuration and Status Registers
      • 6.6.3.1 DC Unlock (DC_UNLOCK)
      • 6.6.3.2 DC General Configuration (DC_GENERAL_CFG)
      • 6.6.3.3 DC Display Configuration (DC_DISPLAY_CFG)
      • 6.6.3.4 DC Arbitration Configuration (DC_ARB_CFG)
    • 6.6.4 Memory Organization Registers
      • 6.6.4.1 DC Frame Buffer Start Address (DC_FB_ST_OFFSET)
      • 6.6.4.2 DC Compression Buffer Start Address (DC_CB_ST_OFFSET)
      • 6.6.4.3 DC Cursor Buffer Start Address (DC_CURS_ST_OFFSET)
      • 6.6.4.4 DC Video Y Buffer Start Address Offset (DC_VID_Y_ST_OFFSET)
      • 6.6.4.5 DC Video U Buffer Start Address Offset (DC_VID_U_ST_OFFSET)
      • 6.6.4.6 DC Video V Buffer Start Address Offset (DC_VID_V_ST_OFFSET)
      • 6.6.4.7 DC Dirty/Valid Region Top (DC_DV_TOP)
      • 6.6.4.8 DC Line Size (DC_LINE_SIZE)
      • 6.6.4.9 DC Graphics Pitch (DC_GFX_PITCH)
      • 6.6.4.10 DC Video YUV Pitch (DC_VID_YUV_PITCH)
    • 6.6.5 Timing Registers
      • 6.6.5.1 DC Horizontal and Total Timing (DC_H_ACTIVE_TIMING)
      • 6.6.5.2 DC CRT Horizontal Blanking Timing (DC_H_BLANK_TIMING)
      • 6.6.5.3 DC CRT Horizontal Sync Timing (DC_H_SYNC_TIMING)
      • 6.6.5.4 DC Vertical and Total Timing (DC_V_ACTIVE_TIMING)
      • 6.6.5.5 DC CRT Vertical Blank Timing (DC_V_BLANK_TIMING)
      • 6.6.5.6 DC CRT Vertical Sync Timing (DC_V_SYNC_TIMING)
      • 6.6.5.7 DC Frame Buffer Active Region Register (DC_FB_ACTIVE)
    • 6.6.6 Cursor Position and Line Count/Status Registers
      • 6.6.6.1 DC Cursor X Position (DC_CURSOR_X)
      • 6.6.6.2 DC Cursor Y Position (DC_CURSOR_Y)
      • 6.6.6.3 DC Line Count/Status (DC_LINE_CNT/STATUS)
    • 6.6.7 Palette Access FIFO Diagnostic Registers
      • 6.6.7.1 DC Palette Address (DC_PAL_ADDRESS)
      • 6.6.7.2 DC Palette Data (DC_PAL_DATA)
      • 6.6.7.3 DC Display FIFO Diagnostic (DC_DFIFO_DIAG)
      • 6.6.7.4 DC Compression FIFO Diagnostic (DC_CFIFO_DIAG)
    • 6.6.8 Video Downscaling
      • 6.6.8.1 DC Video Downscaling Delta (DC_VID_DS_DELTA)
    • 6.6.9 GLIU Control Registers
      • 6.6.9.1 DC GLIU0 Memory Offset (DC_GLIU0_MEM_OFFSET)
      • 6.6.9.2 DC Dirty/Valid RAM Control (DC_DV_CTL)
      • 6.6.9.3 DC Dirty/Valid RAM Access (DC_DV_ACCESS)
    • 6.6.10 Graphics Scaling Control Registers
      • 6.6.10.1 DC Graphics Filter Scale (DC_GFX_SCALE)
      • 6.6.10.2 DC IRQ/Filter Control (DC_IRQ_FILT_CTL)
      • 6.6.10.3 DC Filter Coefficient Data Register 1 (DC_FILT_COEFF1)
      • 6.6.10.4 DC Filter Coefficient Data Register 2 (DC_FILT_COEFF2)
    • 6.6.11 VBI Control Registers
      • 6.6.11.1 DC VBI Even Control (DC_VBI_EVEN_CTL)
      • 6.6.11.2 DC VBI Odd Control (DC_VBI_ODD_CTL)
      • 6.6.11.3 DC VBI Horizontal Control (DC_VBI_HOR)
      • 6.6.11.4 DC VBI Odd Line Enable (DC_VBI_LN_ODD)
      • 6.6.11.5 DC VBI Even Line Enable (DC_VBI_LN_EVEN)
      • 6.6.11.6 DC VBI Pitch and Size (DC_VBI_PITCH)
    • 6.6.12 Color Key Control Registers
      • 6.6.12.1 DC Color Key (DC_CLR_KEY)
      • 6.6.12.2 DC Color Key Mask (DC_CLR_KEY_MASK)
      • 6.6.12.3 DC Color Key Horizontal Position (DC_CLR_KEY_X)
      • 6.6.12.4 DC Color Key Vertical Position (DC_CLR_KEY_Y)
      • 6.6.12.5 DC Interrupt (DC_IRQ)
    • 6.6.13 Interrupt and GenLock Registers
      • 6.6.13.1 DC GenLock Control (DC_GENLK_CTL)
    • 6.6.14 Even Field Video Address Registers
      • 6.6.14.1 DC Even Field Video Y Start Address Offset (DC_VID_EVEN_Y_ST_OFFSET)
      • 6.6.14.2 DC Even Field Video U Start Address Offset (DC_VID_EVEN_U_ST_OFFSET)
      • 6.6.14.3 DC Even Field Video V Start Address Offset (DC_VID_EVEN_V_ST_OFFSET)
    • 6.6.15 Even Field Vertical Timing Registers
      • 6.6.15.1 DC Vertical and Total Timing for Even Fields (DC_V_ACTIVE_EVEN_TIMING)
      • 6.6.15.2 DC CRT Vertical Blank Timing for Even Fields (DC_V_BLANK_EVEN_TIMING)
      • 6.6.15.3 DC CRT Vertical Sync Timing for Even Fields (DC_V_SYNC_EVEN_TIMING)
    • 6.6.16 VGA Block Configuration Registers
      • 6.6.16.1 VGA Configuration (VGA_CONFIG)
      • 6.6.16.2 VGA Status (VGA_STATUS)
    • 6.6.17 VGA Block Standard Registers
      • 6.6.17.1 VGA Miscellaneous Output
      • 6.6.17.2 VGA Input Status Register 0
      • 6.6.17.3 VGA Input Status Register 1
      • 6.6.17.4 VGA Feature Control
    • 6.6.18 VGA Sequencer Registers
      • 6.6.18.1 VGA Sequencer Index
      • 6.6.18.2 VGA Sequencer Data
      • 6.6.18.3 VGA Reset
      • 6.6.18.4 VGA Clocking Mode
      • 6.6.18.5 VGA Map Mask
      • 6.6.18.6 VGA Character Map Select
      • 6.6.18.7 VGA Memory Mode
    • 6.6.19 VGA CRT Controller Registers
      • 6.6.19.1 CRTC Index
      • 6.6.19.2 CRTC Data
      • 6.6.19.3 Horizontal Total
      • 6.6.19.4 Horizontal Display Enable End
      • 6.6.19.5 Horizontal Blank Start
      • 6.6.19.6 Horizontal Blank End
      • 6.6.19.7 Horizontal Sync Start
      • 6.6.19.8 Horizontal Sync End
      • 6.6.19.9 Vertical Total
      • 6.6.19.10 Overflow
      • 6.6.19.11 Preset Row Scan
      • 6.6.19.12 Maximum Scan Line
      • 6.6.19.13 Cursor Start
      • 6.6.19.14 Cursor End
      • 6.6.19.15 Start Address High
      • 6.6.19.16 Start Address Low
      • 6.6.19.17 Cursor Location High
      • 6.6.19.18 Cursor Location Low
      • 6.6.19.19 Vertical Sync Start
      • 6.6.19.20 Vertical Sync End
      • 6.6.19.21 Vertical Display Enable End
      • 6.6.19.22 Offset
      • 6.6.19.23 Underline Location
      • 6.6.19.24 Vertical Blank Start
      • 6.6.19.25 Vertical Blank End
      • 6.6.19.26 CRTC Mode Control
      • 6.6.19.27 Line Compare
      • 6.6.19.28 CPU Data Latch State
      • 6.6.19.29 Attribute Index/Data FF State
      • 6.6.19.30 Attribute Index State
    • 6.6.20 VGA Graphics Controller Registers
      • 6.6.20.1 VGA Graphics Controller Index
      • 6.6.20.2 VGA Graphics Controller Data
      • 6.6.20.3 VGA Set/Reset
      • 6.6.20.4 VGA Enable Set/Reset
      • 6.6.20.5 VGA Color Compare
      • 6.6.20.6 VGA Data Rotate
      • 6.6.20.7 VGA Read Map Select
      • 6.6.20.8 VGA Graphics Mode
      • 6.6.20.9 VGA Miscellaneous
      • 6.6.20.10 VGA Color Don’t Care
      • 6.6.20.11 VGA Bit Mask
    • 6.6.21 Attribute Controller Registers
      • 6.6.21.1 Attribute Controller Index/Data
      • 6.6.21.2 EGA Palette
      • 6.6.21.3 Attribute Mode Control
      • 6.6.21.4 Overscan Color
      • 6.6.21.5 Color Plane Enable
      • 6.6.21.6 Horizontal Pel Panning
      • 6.6.21.7 Color Select
    • 6.6.22 Video DAC Registers
      • 6.6.22.1 Video DAC Palette Address
      • 6.6.22.2 Video DAC State
      • 6.6.22.3 Video DAC Palette Data
      • 6.6.22.4 Video DAC Palette Mask
    • 6.6.23 VGA Block Extended Registers
      • 6.6.23.1 ExtendedRegisterLock
      • 6.6.23.2 ExtendedModeControl
      • 6.6.23.3 ExtendedStartAddress
      • 6.6.23.4 WriteMemoryAperture
      • 6.6.23.5 ReadMemoryAperture
      • 6.6.23.6 BlinkCounterCtl
      • 6.6.23.7 BlinkCounter
      • 6.6.23.8 VGALatchSavRes
      • 6.6.23.9 DACIFSavRes
  • 6.7 Video Processor
    • 6.7.1 Architecture Overview
    • 6.7.2 Functional Description
      • 6.7.2.1 Video Formatter
      • 6.7.2.2 4x4 Filter/Scaler
      • 6.7.2.3 Horizontal Downscaling
    • 6.7.3 X and Y Upscaler
    • 6.7.4 Color Space Converter
    • 6.7.5 Video Overlay
      • 6.7.5.1 Alpha-Blending
      • 6.7.5.2 Gamma RAM
      • 6.7.5.3 Video Processor Module Display Interface
      • 6.7.5.4 Video Interface
    • 6.7.6 Video Output Port
      • 6.7.6.1 Functional Overview
      • 6.7.6.2 Supported Features
      • 6.7.6.3 HBLANK and VBLANK Signals
      • 6.7.6.4 Interface to Video Processor
      • 6.7.6.5 Operating Modes
      • 6.7.6.6 New VIP 2.0 Video Flags
      • 6.7.6.7 BT.601 Support
      • 6.7.6.8 VIP 2.0 Level System
      • 6.7.6.9 VBI Data
    • 6.7.7 Flat Panel Display Controller
      • 6.7.7.1 FP Functional Overview
      • 6.7.7.2 FP Architecture Overview
      • 6.7.7.3 FP Functional Description
    • 6.7.8 VP Resolution Table
    • 6.7.9 Display RGB Modes
  • 6.8 Video Processor Register Descriptions
    • 6.8.1 Standard GeodeLink™ Device MSRs
      • 6.8.1.1 GLD Capabilities MSR (GLD_MSR_CAP)
      • 6.8.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG)
      • 6.8.1.3 GLD SMI MSR (GLD_MSR_SMI)
      • 6.8.1.4 GLD Error MSR (GLD_MSR_ERROR)
      • 6.8.1.5 GLD Power Management MSR (GLD_MSR_PM)
      • 6.8.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG)
    • 6.8.2 Video Processor Module Specific MSRs
      • 6.8.2.1 VP Diagnostic MSR (MSR_DIAG_VP)
      • 6.8.2.2 Pad Select MSR (MSR_PADSEL)
    • 6.8.3 Video Processor Module Control/Configuration Registers
      • 6.8.3.1 Video Configuration (VCFG)
      • 6.8.3.2 Display Configuration (DCFG)
      • 6.8.3.3 Video X Position (VX)
      • 6.8.3.4 Video Y Position (VY)
      • 6.8.3.5 Video Scale (SCL)
      • 6.8.3.6 Video Color Key Register (VCK)
      • 6.8.3.7 Video Color Mask (VCM)
      • 6.8.3.8 Palette Address (PAR)
      • 6.8.3.9 Palette Data (PDR)
      • 6.8.3.10 Saturation Scale (SLR)
      • 6.8.3.11 Miscellaneous (MISC)
      • 6.8.3.12 CRT Clock Select (CCS)
      • 6.8.3.13 Video Y Scale (VYS)
      • 6.8.3.14 Video X Scale (VXS)
      • 6.8.3.15 Video Downscaler Control (VDC)
      • 6.8.3.16 CRC Signature (CRC)
      • 6.8.3.17 32-Bit CRC Signature (CRC32)
      • 6.8.3.18 Video De-Interlacing and Alpha Control (VDE)
      • 6.8.3.19 Cursor Color Key (CCK)
      • 6.8.3.20 Cursor Color Mask (CCM)
      • 6.8.3.21 Cursor Color 1 (CC1)
      • 6.8.3.22 Cursor Color 2 (CC2)
      • 6.8.3.23 Alpha Window 1 X Position (A1X)
      • 6.8.3.24 Alpha Window 1 Y Position (A1Y)
      • 6.8.3.25 Alpha Window 1 Color (A1C)
      • 6.8.3.26 Alpha Window 1 Control (A1T)
      • 6.8.3.27 Alpha Window 2 X Position (A2X)
      • 6.8.3.28 Alpha Window 2 Y Position (A2Y)
      • 6.8.3.29 Alpha Window 2 Color (AC2)
      • 6.8.3.30 Alpha Window 2 Control (A2T)
      • 6.8.3.31 Alpha Window 3 X Position (A3X)
      • 6.8.3.32 Alpha Window 3 Y Position (A3Y)
      • 6.8.3.33 Alpha Window 3 Color (A3C)
      • 6.8.3.34 Alpha Window 3 Control (A3T)
      • 6.8.3.35 Video Request (VRR)
      • 6.8.3.36 Alpha Watch (AWT)
      • 6.8.3.37 Video Processor Test Mode (VTM)
      • 6.8.3.38 Even Video Y Position (VYE)
      • 6.8.3.39 Even Alpha Window 1 Y Position (A1YE)
      • 6.8.3.40 Even Alpha Window 2 Y Position (A2YE)
      • 6.8.3.41 Even Alpha Window 3 Y Position (A3YE)
      • 6.8.3.42 Video Coefficient RAM (VCR)
      • 6.8.3.43 Panel Timing Register 1 (PT1)
      • 6.8.3.44 Panel Timing Register 2 (PT2)
      • 6.8.3.45 Power Management (PM)
      • 6.8.3.46 Dither and Frame Rate Control (DFC)
      • 6.8.3.47 Dither RAM Control and Address (DCA)
      • 6.8.3.48 Dither Memory Data (DMD)
      • 6.8.3.49 Panel CRC Signature (CRC)
      • 6.8.3.50 32-Bit Panel CRC (CRC32)
      • 6.8.3.51 Video Output Port Configuration (VOP_CONFIG)
      • 6.8.3.52 Video Output Port Signature (VOP_SIG)
  • 6.9 Video Input Port
    • 6.9.1 Features
      • 6.9.1.1 Performance Metrics
    • 6.9.2 VIP Block Descriptions
      • 6.9.2.1 Input Formatter
      • 6.9.2.2 Input Control
      • 6.9.2.3 VIP Capture RAM
      • 6.9.2.4 VIP Register Block
      • 6.9.2.5 GLIU Interface
    • 6.9.3 Functional Description
    • 6.9.4 VIP Operation Modes
    • 6.9.5 Mode 1a,b,c - VIP Input Data (simplified BT.656)
      • 6.9.5.1 SAV/EAV Packets
      • 6.9.5.2 Ancillary Packets
    • 6.9.6 Message Passing Mode
    • 6.9.7 Data Streaming Mode
    • 6.9.8 BT.601 Mode
    • 6.9.9 YUV 4:2:2 to YUV 4:2:0 Translation
    • 6.9.10 Software Model
      • 6.9.10.1 Video Data Buffers
      • 6.9.10.2 VBI Data Buffers
      • 6.9.10.3 Ancillary Data Buffers
      • 6.9.10.4 Message Passing/Data Streaming Modes
    • 6.9.11 Bob and Weave
      • 6.9.11.1 Bob
      • 6.9.11.2 Weave
    • 6.9.12 VIP Interrupts
    • 6.9.13 VIP Input Video Status
  • 6.10 Video Input Port Register Descriptions
    • 6.10.1 Standard GeodeLink™ Device (GLD) MSRs
      • 6.10.1.1 GLD Capabilities MSR (GLD_MSR_CAP)
      • 6.10.1.2 GLD Configuration MSR (GLD_MSR_CONFIG)
      • 6.10.1.3 GLD SMI MSR (GLD_MSR_SMI)
      • 6.10.1.4 GLD Error MSR (GLD_MSR_ERROR)
      • 6.10.1.5 GLD Power Management Register (GLD_MSR_PM)
      • 6.10.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG)
    • 6.10.2 VIP Control/Configuration Registers
      • 6.10.2.1 VIP Control Register 1 (VIP_CTL_REG1)
      • 6.10.2.2 VIP Control Register 2 (VIP_CTL_REG2)
      • 6.10.2.3 VIP Status (VIP_STATUS)
      • 6.10.2.4 VIP Interrupt (VIP_INT)
      • 6.10.2.5 VIP Current/Target (VIP_CUR_TAR)
      • 6.10.2.6 VIP Max Address (VIP_MAX_ADDR)
      • 6.10.2.7 VIP Task A Video Even Base Address (VIP_TASK_A_VID_EVEN_BASE)
      • 6.10.2.8 VIP Task A Video Odd Base Address (VIP_TASK_A_VID_ODD_BASE)
      • 6.10.2.9 VIP Task A VBI Even Base Address (VIP_TASK_A_VBI_EVEN_BASE)
      • 6.10.2.10 VIP Task A VBI Odd Base Address (VIP_TASK_A_VBI_ODD_BASE)
      • 6.10.2.11 VIP Task A Video Pitch (VIP_TASK_A_VID_PITCH)
      • 6.10.2.12 VIP Control Register 3 (VIP_CONTRL_REG3)
      • 6.10.2.13 VIP Task A V Offset (VIP_TASK_A_V_OFFSET)
      • 6.10.2.14 VIP Task A U Offset (VIP_TASK_A_U_OFFSET)
      • 6.10.2.15 VIP Task B Video Even Base/Horizontal End (VIP_TASK_B_VID_EVEN_BASE_HORIZ_END)
      • 6.10.2.16 VIP Task B Video Odd Base/Horizontal Start (VIP_TASK_B_VID_ODD_BASE_HORIZ_START)
      • 6.10.2.17 VIP Task B VBI Even Base/VBI End (VIP_TASK_B_VBI_EVEN_BASE_VBI_END)
      • 6.10.2.18 VIP Task B VBI Odd Base/VBI Start (VIP_TASK_B_VBI_ODD_BASE_VBI_START)
      • 6.10.2.19 VIP Task B Data Pitch/Vertical Start Even (VIP_TASK_B_DATA_PITCH_VERT_START_EVEN)
      • 6.10.2.20 VIP Task B V Offset (VIP_TASK_B_V_Offset)
      • 6.10.2.21 VIP Task B U Offset (VIP_TASK_B_U_OFFSET)
      • 6.10.2.22 VIP Ancillary Data/Message Passing/Data Streaming Buffer1 Base Address (VIP_ANC_MSG_1_BASE)
      • 6.10.2.23 VIP Ancillary Data/Message Passing/Data Streaming Buffer 2 Base Address (VIP_ANC_MSG_2_BASE)
      • 6.10.2.24 VIP Ancillary Data/Message Passing/Data Streaming Buffer Size (VIP_ANC_MSG_SIZE)
      • 6.10.2.25 VIP Page Offset/ Page Count (VIP_PAGE_OFFSET)
      • 6.10.2.26 VIP Vertical Start/Stop (VIP_VERT_START_STOP)
      • 6.10.2.27 VIP FIFO Address (VIP_FIFO_R_W_ADDR)
      • 6.10.2.28 VIP FIFO Data (VIP_FIFO_DATA)
      • 6.10.2.29 VIP VSYNC Error Count (VIP_SYNC_ERR_COUNT)
      • 6.10.2.30 VIP Task A U Even Offset (VIP_TASK_A_U_EVEN_OFFSET)
      • 6.10.2.31 VIP Task A V Even Offset (VIP_TASK_A_V_EVEN_OFFSET)
  • 6.11 Security Block
    • 6.11.1 Security Block Features
      • 6.11.1.1 Performance Metrics
    • 6.11.2 Functional Description
      • 6.11.2.1 EEPROM ID Interface
      • 6.11.2.2 Security Block Interrupts
      • 6.11.2.3 GLIU Interface
  • 6.12 Security Block Register Descriptions
    • 6.12.1 Standard GeodeLink™ (GLD) Device MSRs
      • 6.12.1.1 GLD Capabilities MSR (GLD_MSR_CAP)
      • 6.12.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG)
      • 6.12.1.3 GLD SMI MSR (GLD_MSR_SMI)
      • 6.12.1.4 GLD Error MSR (GLD_MSR_ERROR)
      • 6.12.1.5 GLD Power Management MSR (GLD_MSR_PM)
      • 6.12.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG)
    • 6.12.2 Security Block Specific MSRs
      • 6.12.2.1 GLD Control MSR (GLD_MSR_CTRL)
    • 6.12.3 Security Block Configuration/Control Registers
      • 6.12.3.1 SB Control A (SB_CTL_A)
      • 6.12.3.2 SB Control B (SB_CTL_B)
      • 6.12.3.3 SB AES Interrupt (SB_AES_INT)
      • 6.12.3.4 SB Source A (SB_SOURCE_A)
      • 6.12.3.5 SB Destination A (SB_DEST_A)
      • 6.12.3.6 SB Length A (SB_LENGTH_A)
      • 6.12.3.7 SB Source B (SB_SOURCE_B)
      • 6.12.3.8 SB Destination B (SB_DEST_B)
      • 6.12.3.9 SB Length B (SB_LENGTH_B)
      • 6.12.3.10 SB Writable Key 0 (SB_WKEY_0)
      • 6.12.3.11 SB Writable Key 1 (SB_WKEY_1)
      • 6.12.3.12 SB Writable Key 2 (SB_WKEY_2)
      • 6.12.3.13 SB Writable Key 3 (SB_WKEY_3)
      • 6.12.3.14 SB CBC Initialization Vector 0 (SB_CBC_IV_0)
      • 6.12.3.15 SB CBC Initialization Vector 1 (SB_CBC_IV_1)
      • 6.12.3.16 SB CBC Initialization Vector 2 (SB_CBC_IV_2)
      • 6.12.3.17 SB CBC Initialization Vector 3 (SB_CBC_IV_3)
      • 6.12.3.18 SB Random Number (SB_RANDOM_NUM)
      • 6.12.3.19 SB Random Number Status (SB_RANDOM_NUM_STATUS)
      • 6.12.3.20 SB EEPROM Command (SB_EEPROM_COMM)
      • 6.12.3.21 SB EEPROM Address (SB_EEPROM_ADDR)
      • 6.12.3.22 SB EEPROM Data (SB_EEPROM_DATA)
      • 6.12.3.23 SB EEPROM Security State (SB_EEPROM_SEC_STATE)
  • 6.13 GeodeLink™ Control Processor
    • 6.13.1 TAP Controller
    • 6.13.2 Reset Logic
    • 6.13.3 Clock Control
      • 6.13.3.1 Power Management
    • 6.13.4 Companion Device Interface
      • 6.13.4.1 GIO_GLIU
      • 6.13.4.2 GIO_SYNC
      • 6.13.4.3 GIO_PCI
  • 6.14 GeodeLink™ Control Processor Register Descriptions
    • 6.14.1 Standard GeodeLink™ Device MSRs
      • 6.14.1.1 GLD Capabilities MSR (GLD_MSR_CAP)
      • 6.14.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG)
      • 6.14.1.3 GLD SMI MSR (GLD_MSR_SMI)
      • 6.14.1.4 GLD Error MSR (GLD_MSR_ERROR)
      • 6.14.1.5 GLD Power Management MSR (GLD_MSR_PM)
      • 6.14.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG)
    • 6.14.2 GLCP Specific MSRs - GLCP Control MSRs
      • 6.14.2.1 GLCP Clock Disable Delay Value (GLCP_CLK_DIS_DELAY)
      • 6.14.2.2 GLCP Clock Mask for Sleep Request (GLCP_PMCLKDISABLE)
      • 6.14.2.3 Chip Fabrication Information (GLCP_FAB)
      • 6.14.2.4 GLCP Global Power Management Controls (GLCP_GLB_PM)
      • 6.14.2.5 GLCP Debug Output from Chip (GLCP_DBGOUT)
      • 6.14.2.6 GLCP Processor Status (GLCP_PROCSTAT)
      • 6.14.2.7 GLCP DOWSER (GLCP_DOWSER)
      • 6.14.2.8 GLCP I/O Delay Controls (GLCP_DELAY_CONTROLS)
      • 6.14.2.9 GLCP Clock Control (GLCP_CLKOFF)
      • 6.14.2.10 GLCP Clock Active (GLCP_CLKACTIVE)
      • 6.14.2.11 GLCP Clock Mask for Debug Clock Stop Action (GLCP_CLKDISABLE)
      • 6.14.2.12 GLCP Clock Active Mask for Suspend Acknowledge (GLCP_CLK4ACK)
      • 6.14.2.13 GLCP System Reset and PLL Control (GLCP_SYS_RSTPLL)
      • 6.14.2.14 GLCP Dot Clock PLL Control (GLCP_DOTPLL)
      • 6.14.2.15 GLCP Debug Clock Control (GLCP_DBGCLKCTL)
      • 6.14.2.16 Chip Revision ID (GLCP_CHIP_REVID)
      • 6.14.2.17 GLCP Control (GLCP_CNT)
      • 6.14.2.18 GLCP Level 2 (GLCP_LVL2)
      • 6.14.2.19 GLCP Throttle or C2 Start Delay (GLCP_TH_SD)
      • 6.14.2.20 GLCP Scale Factor (GLCP_TH_SF)
      • 6.14.2.21 GLCP Processor Throttle Off Delay (GLCP_TH_OD)
    • 6.14.3 GLCP IGNNE I/Os
    • 6.14.4 GLCP Specific MSRs - GLCP Debug Interface MSRs
      • 6.14.4.1 GLCP DAC (GLCP_DAC)
    • 6.14.5 GLCP Specific MSRs - GLCP Companion Device Interface MSRs
      • 6.14.5.1 CPU A20M Signal (MSR_A20M)
      • 6.14.5.2 CPU INIT Signal (MSR_INIT)
      • 6.14.5.3 GLIU Device Interrupt Status (MSR_INTAX)
  • 6.15 GeodeLink™ PCI Bridge
    • 6.15.1 GeodeLink™ Interface Block
    • 6.15.2 FIFO/Synchronization Block
    • 6.15.3 Transaction Forwarding Block
      • 6.15.3.1 Atomic External MSR Access
    • 6.15.4 PCI Bus Interface Block
      • 6.15.4.1 PCI Configuration and Virtual PCI Header Support
    • 6.15.5 PCI Arbiter
    • 6.15.6 Exception Handling
      • 6.15.6.1 Out-Bound Write Exceptions
      • 6.15.6.2 Out-Bound Read Exceptions
      • 6.15.6.3 In-Bound Write Exceptions
      • 6.15.6.4 In-Bound Read Exceptions
  • 6.16 GeodeLink™ PCI Bridge Register Descriptions
    • 6.16.1 Standard GeodeLink™ Device (GLD) MSRs
      • 6.16.1.1 GLD Capabilities MSR (GLD_MSR_CAP)
      • 6.16.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG)
      • 6.16.1.3 GLD SMI MSR (GLD_MSR_SMI)
      • 6.16.1.4 GLD Error MSR (GLD_MSR_ERROR)
      • 6.16.1.5 GLD Power Management MSR (GLD_MSR_PM)
      • 6.16.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG)
    • 6.16.2 GLPCI Specific Registers
      • 6.16.2.1 GLPCI Global Control (GLPCI_CTRL)
      • 6.16.2.2 GLPCI Arbiter Control (GLPCI_ARB)
      • 6.16.2.3 GLPCI VPH / PCI Configuration Cycle Control (GLPCI_PBUS)
      • 6.16.2.4 GLPCI Debug Packet Configuration (GLPCI_DEBUG)
      • 6.16.2.5 GLPCI Fixed Region Enables (GLPCI_REN)
      • 6.16.2.6 GLPCI Fixed Region Configuration A0-BF (GLPCI_A0)
      • 6.16.2.7 GLPCI Fixed Region Configuration C0-DF (GLPCI_C0)
      • 6.16.2.8 GLPCI Fixed Region Configuration E0-FF (GLPCI_E0)
      • 6.16.2.9 GLPCI Memory Region 0 Configuration (GLPCI_R0)
      • 6.16.2.10 GLPCI Memory Region 1 Configuration (GLPCI_R1)
      • 6.16.2.11 GLPCI Memory Region 2 Configuration (GLPCI_R2)
      • 6.16.2.12 GLCPI Memory Region 3 Configuration (GLPCI_R3)
      • 6.16.2.13 GLCPI Memory Region 4 Configuration (GLPCI_R4)
      • 6.16.2.14 GLPCI Memory Region 5 Configuration (GLPCI_R5)
      • 6.16.2.15 GLPCI External MSR Access Configuration (GLPCI EXT_MSR)
      • 6.16.2.16 GLPCI Spare
      • 6.16.2.17 GLPCI General Purpose I/O (GLPCI_GPIO)
• Electrical Specifications
  • 7.1 Electrical Connections
    • 7.1.1 PWR/GND Connections and Decoupling
    • 7.1.2 NC-Designated Balls
    • 7.1.3 Unused Inputs
  • 7.2 Absolute Maximum Ratings
  • 7.3 Operating Conditions
  • 7.4 DC Current
    • 7.4.1 Power State Parameter Definitions
    • 7.4.2 Definition and Measurement Techniques of Current Parameters
    • 7.4.3 DC Current Measurements
  • 7.5 DC Characteristics
  • 7.6 AC Characteristics
• Instruction Set
  • 8.1 General Instruction Set Format
    • 8.1.1 Prefix (Optional)
    • 8.1.2 Opcode
      • 8.1.2.1 w Field (Operand Size)
      • 8.1.2.2 d Field (Operand Direction)
      • 8.1.2.3 s Field (Immediate Data Field Size)
      • 8.1.2.4 eee Field (MOV-Instruction Register Selection)
    • 8.1.3 mod and r/m Byte (Memory Addressing)
    • 8.1.4 reg Field
      • 8.1.4.1 sreg2 Field (ES, CS, SS, DS Register Selection)
      • 8.1.4.2 sreg3 Field (FS and GS Segment Register Selection)
    • 8.1.5 s-i-b Byte (Scale, Indexing, Base)
      • 8.1.5.1 ss Field (Scale Selection)
      • 8.1.5.2 Index Field (Index Selection)
      • 8.1.5.3 Base Field (s-i-b Present)
  • 8.2 CPUID Instruction Set
    • 8.2.1 Standard CPUID Levels
      • 8.2.1.1 CPUID Instruction with EAX = 00000000h
      • 8.2.1.2 CPUID Instruction with EAX = 00000001h
    • 8.2.2 Extended CPUID Levels
      • 8.2.2.1 CPUID Instruction with EAX = 80000000h
      • 8.2.2.2 CPUID Instruction with EAX = 80000001h
      • 8.2.2.3 CPUID Instruction with EAX = 80000002h, 80000003h, or 80000004h
      • 8.2.2.4 CPUID Instruction with EAX = 80000005h
      • 8.2.2.5 CPUID Instruction with EAX = 80000006h
  • 8.3 Processor Core Instruction Set
    • 8.3.1 Opcodes
    • 8.3.2 Clock Counts
    • 8.3.3 Flags
    • 8.3.4 Non-Standard Processor Core Instructions
      • 8.3.4.1 DMINT - Enter Debug Management Mode
      • 8.3.4.2 ICEBP - Call Debug Exception Handler
      • 8.3.4.3 MOV - Move to/from Test Registers
      • 8.3.4.4 RDM - Leave Debug Management Mode
      • 8.3.4.5 RSDC - Restore Segment Register and Descriptor
      • 8.3.4.6 RSLDT - Restore Local Descriptor Table Register and Descriptor
      • 8.3.4.7 RSM - Leave System Management Mode
      • 8.3.4.8 RSTS - Restore Task Register and Descriptor
      • 8.3.4.9 SETALC - Set AL to CF
      • 8.3.4.10 SMINT - Enter System Management Mode
      • 8.3.4.11 Exceptions
      • 8.3.4.12 SVDC - Save Segment Register and Descriptor
      • 8.3.4.13 SVLDT - Save Local Descriptor Table Register and Descriptor
      • 8.3.4.14 SVTS - Save Task Register and Descriptor
  • 8.4 MMX™, FPU, and AMD 3DNow!™ Technology Instructions Sets
    • 8.4.1 Non-Standard AMD 3DNow!™ Technology Instructions
      • 8.4.1.1 PFRCPV - Floating-Point Reciprocal Approximation
      • 8.4.1.2 PFRSQRTV - Floating-Point Reciprocal Square Root Approximation
• Package Specifications
  • 9.1 Physical Dimensions
• Support Documentation
  • A.1 Order Information
  • A.2 Data Book Revision History