Handling timing violation in mpr states (ddr4) – Teledyne LeCroy Kibra DDR User Manual
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Kibra DDR Protocol Analyzer User Manual
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Recording Options Setup
Teledyne LeCroy
Check the Detailed Mode check‐box to view how the violations are calculated (see
Figure 2.24: Timing Violation Detailed Mode
Handling Timing Violation in MPR states (DDR4)
In DDR4 MPR states, timing violation’s (tRTR, tWTW, tRTW..) values are calculated
according to new formulas and are not same as the normal read/write timing violations in
active states.
The DDR Suite handles all required calculations in the MPR state when Follow MRS
Settings mode is On and shows trigger violations according to the requirements in the
MPR state.
When Follow MRS Settings mode is Off, the software will disable the timing violation
engine during MPR state to prevent any detection of invalid violations.