IEI Integration PICOe-945GSE - Manual (Page 40)

PICOe-945GSE Half-Size CPU Card
Page 40
Supports IEEE 802.1P Layer 2 Priority Encoding
Supports IEEE 802.1Q VLAN tagging
Serial EEPROM
Transmit/Receive on-chip buffer support
Supports power down/link down power saving
Supports PCI MSI (Message Signaled Interrupt) and MSI-X
Supports Receive-Side Scaling (RSS)
2.5.5 Intel
®
ICH7-M PCIe Bus
The Intel® ICH7-M chipset has four PCIe lanes. The four PCIe lanes are interfaced
through a golden finger on the bottom of the CPU card through a compatible half-size
backplane to either four PCIe x1 expansion cards or one PCIe x4 expansion card on. The
PCIe x4 golden finger is shown in
724H
Figure 2-11 below.
Figure 2-11: PCIe x4 Golden finger