Elitegroup PMI8M (V2.0) - Manual (Page 37)

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Using BIOS
DRAM Data Integrity Mode (Non-ECC)
This item is used to configure your RAM’s data integrity mode.
Memory Frequency For (Auto)
This item sets the main memory frequency. When you used an external graphics
card, you can adjust this to enable the best performance for your system.
System BIOS Cacheable (Disabled)
This item allows the system to be cached in memory for faster execution. Enable this
item for better performance.
Video BIOS Cacheable (Disabled)
When this is enabled, the Video RAM will be cached resulting to better performance.
However, if any program was written to this memory area, this may result to system
error.
Delayed Transaction (Enabled)
The chipset has an embedded 32-bit posted write buffer to support delayed transac-
tion cycles. Enable this item to support compliance with PCI specification version
2.1.
Delay Prior to Thermal (16 Min)
Enables you to set the delay time before the CPU enters auto thermal mode.
AGP Aperture Size (MB) (128)
This item defines the size of the aperture if you use an AGP graphics adapter. The
AGP aperture refers to a section of the PCI memory address range used for graphics
memory. We recommend that you leave this item at the default value.
On-Chip VGA (Enabled)
Enables and disables the built-in on-chip VGA.
On-Chip Frame Buffer Size (8M)
This item allows you to set the VGA frame buffer size.
Boot Display (VBIOS Default)
This item is for Intel define ADD card only.
Panel Number (1)
This item is used to select the number to support LVDS panel.
• DRAM RAS# Precharge (3): Select the number of CPU clocks allo-
cated for the Row Address Strobe (RAS#) signal to accumulate its
charge before the DRAM is refreshed. If insufficient time is allowed,
refresh may be incomplete and data lost.
• CAS Latency Time (2.5): This item controls the timing delay (in clock
cycles) before the DRAM starts a read command after receiving it.
• Active to Precharge Delay (7): This precharge time is the number of
cycles it takes for DRAM to accumulate its charge before refresh.
• DRAM RAS# to CAS# Delay (3): This field lets you insert a timing delay
between the CAS and RAS strobe signals, used when DRAM is writ-
ten to, read from, or refreshed. Disabled gives faster performance;
and Enabled gives more stable performance.