Cirrus Logic AN379 - Manual (Page 19)

AN379
AN379REV2 19
resistor R
CLAMP
must comply with the relation defined in Equation 38:
Using the denominators of Equations 37 and 38, the inequality P
Target
≥ 45.5

P
OUT(min)
can be used to
determine which function will determine the sizing of clamp resistor R
CLAMP
. With a minimum dim level that is
less than 6.5%, this inequality will almost always be true and the first function will define the clamp
resistor R
CLAMP
. If a minimum dim level is 8% or greater, the inequality will almost always be false and the
second function will define the clamp resistor R
CLAMP
.
A clamp circuit design criteria states that the clamp resistance must have a minimum rating of 2W. Clamp
voltage V
CLAMP
is used to define power level P
OPP
at which OPP trips. Clamp resistor R
CLAMP
must be
designed so the minimum trip point for OPP is 2W when the clamp circuit is turned on for a maximum duty
cycle

CLAMP(on)
of 10%. Check that clamp resistor R
CLAMP
meets this condition using Equation 39:
3.5 Completing the Design
Step 19) Choose Power Components
The voltage rating of boost FET Q
BST
and diode D
BST
can be estimated by adding 20% to voltage V
BST
.
Adding 20% is a standard margin for safety purposes and prevents damage to the components during
abnormal or transient conditions. Lower voltage ratings can be used, but sufficient testing is necessary to
ensure proper operation.
Boost output voltage V
BST
is 28V for an AC input voltage of 12VAC. The breakdown voltage for both the
FET Q
BST
and the boost diode D
BST
≥ (1.2  V
BST
). The boost diode must be ultrafast with a recovery time no
greater than 50ns and rated for a DC current, as calculated using Equation 25 on page 15.
Step 20) Startup Circuit and Steady State Supply
The startup circuit is constructed of a linear regulator and charge pump and is used to supply a power-on
voltage to the CS1680. The device provides a GPIO pin that is used to disable the startup circuit once the boost
output voltage reaches 50% of full scale.
The linear regulator circuit is built using resistor R3, zener diode D9, capacitor C4, and transistor Q4 to provide
a supply voltage to a Schmitt-trigger inverter U2. The GPIO pin is tri-stated while the controller is held in reset
due to low supply voltage. Inverter U2 enables the charge pump circuit, which is built using diodes D13 and
D11, capacitors C5 and C9, resistors R12 and R4 and inverter U2. Initial supply current I
DD
flows through
resistor R13 and zener diode D7, which is immediately biased, driving transistor Q5 into conduction to provide
a start-up voltage to pin VDD. The charge pump increases the voltage until the device starts converting. Once
the supply voltage V
DD
exceeds threshold voltage V
ST(th)
, the controller polls the boost output voltage for 50%
of full scale before driving the GPIO pin low to disable the startup circuit. The boost output voltage provides a
sufficient voltage to keep transistor Q5 into conduction and to supply a voltage across capacitor C21.
Step 21) External Overtemperature Protection
The external overtemperature protection (eOTP) pin is used to implement overtemperature protection. A
negative temperature coefficient (NTC) thermistor resistive network is connected to pin eOTP, usually in the
form of a series combination of a resistor R
S
and a thermistor R
NTC
. The CS1680 cyclically samples the
resistance connected to pin eOTP.
The CS1680 recognizes a resistance (R
S
+R
NTC
) equal to 20.3k which corresponds to a temperature of
95°C, as the beginning of an overtemperature dimming event and starts reducing the power dissipation. The
output current is scaled until the resistance (R
S
+R
NTC
) value reaches 16.26k  (125°C). Beyond this
temperature, the IC enters a fault state and shuts down. This fault state is a latched protection state, and the fault
state is not cleared until the power to the IC is recycled.
R
CLAMP
0.022 V
CLAMP
2

P
OUT min  
-------------------------------------------
V
BST full  
K
CLAMP on  
  
2
45.5 P
OUT min  

---------------------------------------------------------------------- =  [Eq. 38]
R
CLAMP

CLAMP on  
V
CLAMP
2 
P
OPP
------------------------------------------------------------
V
BST full  
K
CLAMP on  
   2
10 P
OPP

---------------------------------------------------------------------- =  [Eq. 39]