Cirrus Logic AN379 - Manual (Page 20)

AN379
20 AN379REV2
Step 22) Layout
Basics for any power layout:
• Keep power traces as short as possible.
• Keep the controller away from power components and traces if possible. Keep sensitive traces (all sense
inputs) away from high dv/dt traces such as FET drain and FET gate drive.
• Decouple the capacitor directly at the VDD pin of the CS1680 to GND.
• Run sense traces, especially current sense, away from power-carrying traces characterized by high dv/dt
(fast rise/fall times) traces such as sources and drains of FETs Q
BST
, Q
CLAMP
, and Q
BUCK
.
• Further details are available in application note AN346 CS150x and CS160x PCB Layout Guidelines.