Cirrus Logic CS2000-CP - Manual (Page 32)

CS2000-CP
32 DS761F2
8.7.2 AUX PLL Lock Output Configuration (AuxLockCfg)
When the AUX_OUT pin is configured as a lock indicator (AuxOutSrc[1:0] = 11), this bit configures the
AUX_OUT driver to either push-pull or open drain. It also determines the polarity of the lock signal. If
AUX_OUT is configured as a clock output, the state of this bit is disregarded.
Note: AUX_OUT is an unlock indicator, signalling an error condition when the PLL is unlocked. There-
fore, the pin polarity is defined relative to the unlock condition.
8.7.3 Reference Clock Input Divider (RefClkDiv[1:0])
Selects the input divider for the timing reference clock.
8.8 Function Configuration 2 (Address 17h)
8.8.1 Enable PLL Clock Output on Unlock (ClkOutUnl)
Defines the state of the PLL output during the PLL unlock condition.
8.8.2 Low-Frequency Ratio Configuration (LFRatioCfg)
Determines how to interpret the currently indexed 32-bit User Defined Ratio when the dynamic ratio based
Hybrid PLL Mode is selected (either manually or automatically, see
section 5.3.5 on page 21 ).
Note: When the static ratio based Frequency Synthesizer Mode is selected (either manually or auto-
matically), the currently indexed User Defined Ratio will always be interpreted as a 12.20 fixed point value,
regardless of the state of this bit.
AuxLockCfg AUX_OUT Driver Configuration
0 Push-Pull, Active High (output ‘high’ for unlocked condition, ‘low’ for locked condition).
1 Open Drain, Active Low (output ‘low’ for unlocked condition, high-Z for locked condition).
Application: “Auxiliary Output” on page 23
RefClkDiv[1:0] Reference Clock Input Divider REF_CLK Frequency Range
00 ÷ 4. 32 MHz to 56 MHz (50 MHz with XTI)
01 ÷ 2. 16 MHz to 28 MHz
10 ÷ 1. 8 MHz to 14 MHz
11 Reserved.
Application: “Internal Timing Reference Clock Divider” on page 14
7 6 5 4 3 2 1 0
Reserved Reserved Reserved ClkOutUnl LFRatioCfg Reserved Reserved Reserved
ClkOutUnl Clock Output Enable Status
0 Clock outputs are driven ‘low’ when PLL is unlocked.
1 Clock outputs are always enabled (results in unpredictable output when PLL is unlocked).
Application: “PLL Clock Output” on page 23
LFRatioCfg Ratio Bit Encoding Interpretation when Input Clock Source is CLK_IN
0 20.12 - High Multiplier.
1 12.20 - High Accuracy.
Application: “User Defined Ratio (RUD), Hybrid PLL Mode” on page 19