Cirrus Logic CS2300-CP - Manual (Page 13)

CS2300-CP
DS843F2 13
5. APPLICATIONS
5.1 Timing Reference Clock
The internal LC oscillator is used to generate the internal timing reference clock (see section 4 “Architecture
Overview” on page 11 for information on how this internal clock is used by the CS2300). A single 0.1 µF cap
must be connected between the FILTP and FILTN pins and the FILTN pin must be connected to ground as
shown in
Figure 9 .
5.2 Frequency Reference Clock Input, CLK_IN
The frequency reference clock input (CLK_IN) is used by the Digital PLL and Fractional-N Logic block to
dynamically generate a fractional-N value for the Frequency Synthesizer (see
“Hybrid Analog-Digital PLL”
on page 12 ). The Digital PLL first compares the CLK_IN frequency to the PLL output. The Fractional-N logic
block then translates the desired ratio based off of CLK_IN to one based off of the internal LCO. This allows
the low-jitter internal LCO to be used as the clock which the Frequency Synthesizer multiplies while main-
taining synchronicity with the frequency reference clock through the Digital PLL. The allowable frequency
range for CLK_IN is found in the
“AC Electrical Characteristics” on page 7 .
5.2.1 CLK_IN Skipping Mode
CLK_IN skipping mode allows the PLL to maintain lock even when the CLK_IN signal has missing pulses
for up to
20 ms (t
CS
) at a time (see “AC Electrical Characteristics” on page 7 for specifications). CLK_IN
skipping mode can only be used when the CLK_IN frequency is below 80 kHz and CLK_IN is reapplied
within 20 ms of being removed. The ClkSkipEn bit enables this function.
Figure 9. External Component Requirements for LCO
FILTN FILTP
C