Cirrus Logic CS2300-CP - Manual (Page 14)

CS2300-CP
14 DS843F2
Regardless of the setting of the ClkSkipEn bit the PLL output will continue for 2
23
LCO cycles (518 ms to
634 ms) after CLK_IN is removed (see Figure 10 ). This is true as long as CLK_IN does not glitch or have
an effective change in period as the clock source is removed, otherwise the PLL will interpret this as a
change in frequency causing clock skipping and the 2
23
LCO cycle time-out to be bypassed and the PLL
to immediately unlock. If the prior conditions are met while CLK_IN is removed and 2
23
LCO cycles pass,
the PLL will unlock and the PLL_OUT state will be determined by the ClkOutUnl bit; See “PLL Clock Out-
put” on page 19 . If CLK_IN is re-applied after such time, the PLL will remain unlocked for the specified
time listed in the “AC Electrical Characteristics” on page 7 after which lock will be acquired and the PLL
output will resume.
If it is expected that CLK_IN will be removed and then reapplied within 2
23
LCO cycles but later than t
CS
,
the ClkSkipEn bit should be disabled. If it is not disabled, the device will behave as shown in Figure 11 ;
note that the lower figure shows that the PLL output frequency may change and be incorrect without an
indication of an unlock condition.
Figure 10. CLK_IN removed for > 2
23
LCO cycles
CLK_IN
PLL_OUT
UNLOCK
ClkSkipEn=0 or 1
ClkOutUnl=0
Lock Time
CLK_IN
PLL_OUT
UNLOCK
ClkSkipEn=0 or 1
ClkOutUnl=1
Lock Time
= invalid clocks
2 23 LCO cycles 2 23 LCO cycles
CLK_IN
PLL_OUT
UNLOCK
ClkSkipEn=0 or 1
ClkOutUnl=0
Lock Time
CLK_IN
PLL_OUT
UNLOCK
ClkSkipEn=0 or 1
ClkOutUnl=1
Lock Time
t
CS
t
CS
= invalid clocks
CLK_IN
PLL_OUT
UNLOCK
ClkSkipEn= 1
ClkOutUnl= 0 or 1
Lock Time
t
CS
= invalid clocks
2 23 LCO cycles 2 23 LCO cycles
2 23 LCO cycles
Figure 11. CLK_IN removed for < 2
23
LCO cycles but > t
CS